{"id":"https://openalex.org/W2465341489","doi":"https://doi.org/10.1109/hotchips.2012.7476494","title":"An IA-32 processor with a wide voltage operating range in 32nm CMOS","display_name":"An IA-32 processor with a wide voltage operating range in 32nm CMOS","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2465341489","doi":"https://doi.org/10.1109/hotchips.2012.7476494","mag":"2465341489"},"language":"en","primary_location":{"id":"doi:10.1109/hotchips.2012.7476494","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2012.7476494","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Hot Chips 24 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108599907","display_name":"Gregory Ruhl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Gregory Ruhl","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061796240","display_name":"Saurabh Dighe","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saurabh Dighe","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090001638","display_name":"Shailendra Jain","orcid":"https://orcid.org/0000-0002-3391-1711"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shailendra Jain","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061392850","display_name":"Surhud Khare","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Surhud Khare","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024748519","display_name":"Satish Yada","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satish Yada","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069951707","display_name":"V Ambili","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V Ambili","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077422345","display_name":"Praveen Salihundam","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Praveen Salihundam","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112328474","display_name":"Shiva Ramani","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shiva Ramani","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071772533","display_name":"Sriram Muthukumar","orcid":"https://orcid.org/0000-0002-8761-7278"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sriram Muthukumar","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101740040","display_name":"M. Srinivasan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M Srinivasan","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100719757","display_name":"Arun Kumar","orcid":"https://orcid.org/0000-0001-8558-6810"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arun Kumar","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100974612","display_name":"Shasi Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shasi Kumar","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081157353","display_name":"R. Ramanarayanan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajaraman Ramanarayanan","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081522570","display_name":"Vasantha Erraguntla","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vasantha Erraguntla","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102833447","display_name":"Jason Howard","orcid":"https://orcid.org/0009-0005-6250-6108"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Howard","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103567305","display_name":"Sriram Vangal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sriram Vangal","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043332479","display_name":"Paolo Aseron","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paolo Aseron","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110035949","display_name":"Howard Wilson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Howard Wilson","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112900267","display_name":"Nitin Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nitin Borkar","raw_affiliation_strings":["Microprocessor & Programming Research, Intel Labs, United States","Microprocessor & Programming Research, Intel Labs"],"affiliations":[{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs, United States","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor & Programming Research, Intel Labs","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":19,"corresponding_author_ids":["https://openalex.org/A5108599907"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.5801,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.70329773,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"37"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9754999876022339,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.7591477632522583},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7102178931236267},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6581746339797974},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5941380858421326},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5405493974685669},{"id":"https://openalex.org/keywords/range","display_name":"Range (aeronautics)","score":0.5078681111335754},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49271777272224426},{"id":"https://openalex.org/keywords/presentation","display_name":"Presentation (obstetrics)","score":0.4433175027370453},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.39103686809539795},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3588266372680664},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29207032918930054},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22965025901794434},{"id":"https://openalex.org/keywords/aerospace-engineering","display_name":"Aerospace engineering","score":0.07316270470619202}],"concepts":[{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.7591477632522583},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7102178931236267},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6581746339797974},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5941380858421326},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5405493974685669},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.5078681111335754},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49271777272224426},{"id":"https://openalex.org/C2777601897","wikidata":"https://www.wikidata.org/wiki/Q3409113","display_name":"Presentation (obstetrics)","level":2,"score":0.4433175027370453},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.39103686809539795},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3588266372680664},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29207032918930054},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22965025901794434},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.07316270470619202},{"id":"https://openalex.org/C126838900","wikidata":"https://www.wikidata.org/wiki/Q77604","display_name":"Radiology","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hotchips.2012.7476494","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2012.7476494","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Hot Chips 24 Symposium (HCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5299999713897705,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2770234245","https://openalex.org/W96612179","https://openalex.org/W4229499248","https://openalex.org/W2566006169","https://openalex.org/W1567818861","https://openalex.org/W2987774938","https://openalex.org/W4256492088","https://openalex.org/W632915154","https://openalex.org/W2055733372","https://openalex.org/W3022067003"],"abstract_inverted_index":{"This":[0],"article":[1],"consists":[2],"of":[3,6,16,25,34,42,55,67],"a":[4,22,53],"collection":[5],"slides":[7],"from":[8],"the":[9,14,35,40,56],"author's":[10],"conference":[11],"presentation":[12],"on":[13],"deployment":[15],"an":[17],"Intel":[18,57],"IA-32":[19],"processor":[20],"with":[21],"wide":[23,47],"range":[24,49],"voltage":[26,45],"operating":[27],"ranges":[28],"in":[29],"32nm":[30],"CMOS":[31],"technology.":[32],"Some":[33],"specific":[36],"topics":[37],"discussed":[38],"include:":[39],"purpose":[41],"near":[43],"threshold":[44],"and":[46,62,64,69],"dynamic":[48],"capabilities;":[50],"design":[51,60],"challenges;":[52],"description":[54],"Claremont":[58],"prototype;":[59],"strategies":[61],"methodologies;":[63],"key":[65],"areas":[66],"product":[68],"system":[70],"improvement":[71]},"counts_by_year":[{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
