{"id":"https://openalex.org/W2461636033","doi":"https://doi.org/10.1109/hotchips.2012.7476473","title":"Roadmap for design and EDA infrastructure for 3D products","display_name":"Roadmap for design and EDA infrastructure for 3D products","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2461636033","doi":"https://doi.org/10.1109/hotchips.2012.7476473","mag":"2461636033"},"language":"en","primary_location":{"id":"doi:10.1109/hotchips.2012.7476473","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2012.7476473","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Hot Chips 24 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015473688","display_name":"Riko Radojcic","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Riko Radojcic","raw_affiliation_strings":["Qualcomm, United States","Qualcomm, Cupertino, CA"],"affiliations":[{"raw_affiliation_string":"Qualcomm, United States","institution_ids":["https://openalex.org/I4210087596"]},{"raw_affiliation_string":"Qualcomm, Cupertino, CA","institution_ids":["https://openalex.org/I4210087596"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5015473688"],"corresponding_institution_ids":["https://openalex.org/I4210087596"],"apc_list":null,"apc_paid":null,"fwci":1.3619,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.84996502,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"21"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10783","display_name":"Additive Manufacturing and 3D Printing Technologies","score":0.9172000288963318,"subfield":{"id":"https://openalex.org/subfields/2203","display_name":"Automotive Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10783","display_name":"Additive Manufacturing and 3D Printing Technologies","score":0.9172000288963318,"subfield":{"id":"https://openalex.org/subfields/2203","display_name":"Automotive Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.7418261766433716},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6576884984970093},{"id":"https://openalex.org/keywords/design-technology","display_name":"Design technology","score":0.5024092197418213},{"id":"https://openalex.org/keywords/computer-automated-design","display_name":"Computer-automated design","score":0.49307796359062195},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.432763934135437},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.42654949426651},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.4178429841995239},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.391074538230896},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36467260122299194},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.33116960525512695},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.2427600622177124},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2244873344898224},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.18744271993637085}],"concepts":[{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.7418261766433716},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6576884984970093},{"id":"https://openalex.org/C179737136","wikidata":"https://www.wikidata.org/wiki/Q5264382","display_name":"Design technology","level":2,"score":0.5024092197418213},{"id":"https://openalex.org/C205976826","wikidata":"https://www.wikidata.org/wiki/Q5157390","display_name":"Computer-automated design","level":3,"score":0.49307796359062195},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.432763934135437},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.42654949426651},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.4178429841995239},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.391074538230896},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36467260122299194},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.33116960525512695},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.2427600622177124},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2244873344898224},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.18744271993637085},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hotchips.2012.7476473","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2012.7476473","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Hot Chips 24 Symposium (HCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2024555067","https://openalex.org/W2038083073","https://openalex.org/W3205162826","https://openalex.org/W2059530328","https://openalex.org/W2080428035","https://openalex.org/W2465693246","https://openalex.org/W2056740847","https://openalex.org/W3001770227","https://openalex.org/W2146629087","https://openalex.org/W2130135927"],"abstract_inverted_index":{"This":[0],"article":[1],"consists":[2],"of":[3,6,28,53],"a":[4],"collection":[5],"slides":[7],"from":[8],"the":[9,14,29,62],"author's":[10],"conference":[11],"presentation":[12],"on":[13,67],"design":[15,18,35,55,57,63],"and":[16,61],"electronic":[17],"automation":[19],"(EDA)":[20],"infrastructure":[21],"for":[22,38,47,59,65],"three-dimensional":[23],"mobile":[24],"display":[25],"products.":[26],"Some":[27],"specific":[30],"topics":[31],"discussed":[32],"include:":[33],"EDA":[34],"methodologies;":[36],"options":[37],"chip":[39],"design;":[40],"memory":[41],"capacity;":[42],"evolving":[43],"3D":[44,48],"technologies;":[45,56],"ecosystems":[46],"designs;":[49],"thermal":[50],"challenges;":[51],"inventories":[52],"core":[54],"environments":[58],"interposers;":[60],"environment":[64],"logic":[66,68],"design.":[69]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}