{"id":"https://openalex.org/W2543069078","doi":"https://doi.org/10.1109/hotchips.2011.7477493","title":"Bandwidth engine\u00ae serial memory chip breaks 2 billion accesses/sec","display_name":"Bandwidth engine\u00ae serial memory chip breaks 2 billion accesses/sec","publication_year":2011,"publication_date":"2011-08-01","ids":{"openalex":"https://openalex.org/W2543069078","doi":"https://doi.org/10.1109/hotchips.2011.7477493","mag":"2543069078"},"language":"en","primary_location":{"id":"doi:10.1109/hotchips.2011.7477493","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2011.7477493","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE Hot Chips 23 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016919908","display_name":"Michael Miller","orcid":"https://orcid.org/0000-0003-1209-5134"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Michael J. Miller","raw_affiliation_strings":["VP Technology Innovation & Systems Applications, MoSys"],"affiliations":[{"raw_affiliation_string":"VP Technology Innovation & Systems Applications, MoSys","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5016919908"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2651,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.82585418,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7037000060081482,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7037000060081482,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7434403896331787},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5997781753540039},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5460408926010132},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5178437829017639},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.49898481369018555},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4935652017593384},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.45474717020988464},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4501960277557373},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4372180104255676},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4149947166442871},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4144187867641449},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38245561718940735},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34633511304855347},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13251984119415283},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07911151647567749}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7434403896331787},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5997781753540039},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5460408926010132},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5178437829017639},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.49898481369018555},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4935652017593384},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.45474717020988464},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4501960277557373},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4372180104255676},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4149947166442871},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4144187867641449},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38245561718940735},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34633511304855347},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13251984119415283},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07911151647567749}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hotchips.2011.7477493","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2011.7477493","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE Hot Chips 23 Symposium (HCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3048967625","https://openalex.org/W2999459628","https://openalex.org/W4248614727","https://openalex.org/W4312264564","https://openalex.org/W2296275612","https://openalex.org/W1975698617","https://openalex.org/W2043352873","https://openalex.org/W2561005478","https://openalex.org/W1554378476","https://openalex.org/W2074563599"],"abstract_inverted_index":{"Presents":[0],"a":[1],"collection":[2],"of":[3],"slides":[4],"covering":[5],"the":[6],"following":[7],"topics:":[8],"network":[9],"memory":[10,15],"access;":[11],"bandwidth":[12],"engine":[13],"design;":[14],"interface;":[16],"and":[17],"multicore":[18],"process.":[19]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
