{"id":"https://openalex.org/W2472491098","doi":"https://doi.org/10.1109/hotchips.2010.7480083","title":"Westmere-EX: A 20 thread server CPU","display_name":"Westmere-EX: A 20 thread server CPU","publication_year":2010,"publication_date":"2010-08-01","ids":{"openalex":"https://openalex.org/W2472491098","doi":"https://doi.org/10.1109/hotchips.2010.7480083","mag":"2472491098"},"language":"en","primary_location":{"id":"doi:10.1109/hotchips.2010.7480083","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2010.7480083","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Hot Chips 22 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018287086","display_name":"Dheemanth Nagaraj","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Dheemanth Nagaraj","raw_affiliation_strings":["Westmere-EX Architecture"],"affiliations":[{"raw_affiliation_string":"Westmere-EX Architecture","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042497106","display_name":"Sailesh Kottapalli","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sailesh Kottapalli","raw_affiliation_strings":["Westmere-EX Architecture"],"affiliations":[{"raw_affiliation_string":"Westmere-EX Architecture","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5018287086"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4994,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.69625133,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"18"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9300000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9300000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.8039216995239258},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7714046835899353},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.6511590480804443},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5105746984481812},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3916858732700348},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35146668553352356}],"concepts":[{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.8039216995239258},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7714046835899353},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.6511590480804443},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5105746984481812},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3916858732700348},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35146668553352356},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hotchips.2010.7480083","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2010.7480083","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Hot Chips 22 Symposium (HCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2033778626","https://openalex.org/W2187110187","https://openalex.org/W2026780467","https://openalex.org/W2002371119","https://openalex.org/W2018697868","https://openalex.org/W4390492895","https://openalex.org/W2886225742","https://openalex.org/W4323662771","https://openalex.org/W1986146167","https://openalex.org/W2038503502"],"abstract_inverted_index":{"This":[0],"article":[1],"consists":[2],"of":[3,6,22,25,39],"a":[4,16],"collection":[5],"slides":[7],"from":[8],"the":[9,26,31,40],"author's":[10],"conference":[11],"presentation":[12],"on":[13],"Intel's":[14],"Westmere-EX,":[15],"20":[17],"thread":[18],"server":[19],"CPU":[20],"family":[21],"products.":[23],"Some":[24],"specific":[27],"topics":[28],"discussed":[29],"include:":[30],"special":[32],"features,":[33],"system":[34,37,42],"specifications,":[35],"and":[36,51],"design":[38],"Westmere-EX;":[41],"architecture;":[43],"applications":[44],"for":[45],"use;":[46],"platforms":[47],"supported;":[48],"processing":[49],"capabilities;":[50],"targeted":[52],"markets.":[53]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
