{"id":"https://openalex.org/W2468283998","doi":"https://doi.org/10.1109/hotchips.2010.7480077","title":"28nm generation programmable families","display_name":"28nm generation programmable families","publication_year":2010,"publication_date":"2010-08-01","ids":{"openalex":"https://openalex.org/W2468283998","doi":"https://doi.org/10.1109/hotchips.2010.7480077","mag":"2468283998"},"language":"en","primary_location":{"id":"doi:10.1109/hotchips.2010.7480077","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2010.7480077","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Hot Chips 22 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010566500","display_name":"Brad Taylor","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Brad Taylor","raw_affiliation_strings":["Division of Biomedical Engineering"],"affiliations":[{"raw_affiliation_string":"Division of Biomedical Engineering","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030738948","display_name":"Ralph Wittig","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ralph Wittig","raw_affiliation_strings":["Xilinx, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5010566500"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.29538099,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9397000074386597,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9397000074386597,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9222999811172485,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7566379308700562},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7406357526779175},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7244868278503418},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.6419613361358643},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.619504988193512},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6122550964355469},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.6064185500144958},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5643125772476196},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.561308741569519},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5447285175323486},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.45726996660232544},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.37900638580322266},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2847379744052887},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17944645881652832},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.16338235139846802},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11272898316383362}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7566379308700562},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7406357526779175},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7244868278503418},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.6419613361358643},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.619504988193512},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6122550964355469},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.6064185500144958},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5643125772476196},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.561308741569519},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5447285175323486},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.45726996660232544},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.37900638580322266},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2847379744052887},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17944645881652832},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.16338235139846802},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11272898316383362},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hotchips.2010.7480077","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2010.7480077","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE Hot Chips 22 Symposium (HCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3013792460","https://openalex.org/W3117015220","https://openalex.org/W4234601000","https://openalex.org/W2151236218","https://openalex.org/W2254425074","https://openalex.org/W2534453537","https://openalex.org/W1512285683","https://openalex.org/W2197466303","https://openalex.org/W2187918628"],"abstract_inverted_index":{"\u25aa":[0,28,53,81],"Unified":[1],"device":[2],"architecture":[3],"for":[4,73],"all":[5],"7":[6,91],"Series":[7,92],"FPGAs":[8,74],"-":[9,18,23,37,42,47,64,69,75,83,90,99],"Scalable":[10],"platform":[11],"with":[12,32,85],"three":[13],"families:":[14],"cost,":[15],"power,":[16],"performance":[17],"50%":[19],"total":[20],"power":[21],"reduction":[22],"Increased":[24],"capacity":[25],"and":[26,51,58,78],"bandwidth":[27],"Xilinx":[29,55],"EPP:":[30,100],"SOC":[31],"embedded":[33],"programmable":[34],"logic":[35],"array":[36],"Boots":[38],"like":[39],"a":[40],"processor":[41],"SW":[43],"centric":[44],"programming":[45],"model":[46],"Extensible":[48],"peripheral":[49],"set":[50],"compute":[52],"All":[54],"IP":[56,84],"(soft":[57],"hard)":[59],"use":[60],"AMBA":[61],"AXI":[62,86],"interconnect":[63,68],"High":[65],"performance,":[66],"scalable":[67],"AXI4":[70],"is":[71],"optimized":[72],"Memory":[76],"mapped":[77],"streaming":[79],"interfaces":[80],"Availability":[82],"interface:":[87],"Sept":[88],"2010":[89],"FPGAs:":[93],"First":[94],"devices":[95],"in":[96],"early":[97],"2011":[98],"To":[101],"Be":[102],"Announced":[103]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
