{"id":"https://openalex.org/W2775449767","doi":"https://doi.org/10.1109/hldvt.2017.8167469","title":"An approach to approximate computing: Logic transformations for one-minterm changes in specification","display_name":"An approach to approximate computing: Logic transformations for one-minterm changes in specification","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2775449767","doi":"https://doi.org/10.1109/hldvt.2017.8167469","mag":"2775449767"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2017.8167469","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2017.8167469","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["Tokyo Daigaku, Bunkyo-ku, Tokyo, JP"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5027837299"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"94"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/truth-table","display_name":"Truth table","score":0.8007766008377075},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6497572660446167},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6226907968521118},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6172844171524048},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5682899355888367},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5539113283157349},{"id":"https://openalex.org/keywords/sort","display_name":"sort","score":0.549582302570343},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5276642441749573},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.49336281418800354},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4903452396392822},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.45927363634109497},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4538669288158417},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.42218634486198425},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41026103496551514},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.38465774059295654},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2976425886154175},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16696038842201233},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10794830322265625},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0781840980052948},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.0728905200958252}],"concepts":[{"id":"https://openalex.org/C56949724","wikidata":"https://www.wikidata.org/wiki/Q219079","display_name":"Truth table","level":2,"score":0.8007766008377075},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6497572660446167},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6226907968521118},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6172844171524048},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5682899355888367},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5539113283157349},{"id":"https://openalex.org/C88548561","wikidata":"https://www.wikidata.org/wiki/Q347599","display_name":"sort","level":2,"score":0.549582302570343},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5276642441749573},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.49336281418800354},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4903452396392822},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.45927363634109497},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4538669288158417},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.42218634486198425},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41026103496551514},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.38465774059295654},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2976425886154175},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16696038842201233},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10794830322265625},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0781840980052948},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0728905200958252},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2017.8167469","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2017.8167469","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G456519342","display_name":"Design methods for high performance-highly reliable systems using auto-backup mechanisms","funder_award_id":"17H01709","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"}],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1528837436","https://openalex.org/W1931835055","https://openalex.org/W1988473863","https://openalex.org/W2014319462","https://openalex.org/W2037862379","https://openalex.org/W2047503989","https://openalex.org/W2564787410","https://openalex.org/W4235567996"],"related_works":["https://openalex.org/W3129977055","https://openalex.org/W1966764473","https://openalex.org/W1488117239","https://openalex.org/W2386022279","https://openalex.org/W659242671","https://openalex.org/W2356140560","https://openalex.org/W2051956260","https://openalex.org/W2356714888","https://openalex.org/W1497518879","https://openalex.org/W1936067987"],"abstract_inverted_index":{"Here":[0],"we":[1,94,130,134],"consider":[2],"one":[3,39,86,142,192,201],"special":[4],"situation":[5],"for":[6,37,74,85,97,126],"approximate":[7,75],"computing.":[8],"Given":[9],"a":[10,14,59,69],"specification,":[11],"S,":[12],"in":[13,57,102,144,172,175,183,195],"truth":[15,34,196],"table":[16,35],"and":[17,152,202],"its":[18,156],"corresponding":[19],"multi-level":[20,237],"logic":[21,76,229],"circuit":[22,119,162],"implementation,":[23],"I,":[24,105,151],"S":[25],"is":[26,63,68],"changed":[27],"to":[28,43,47,52,65,124,136,154,165,180,218],"S'":[29,66,125,166],"by":[30],"only":[31,141],"changing":[32,107],"the":[33,79,100,103,118,128,138,145,149,161,170,181,184,210,214,221,232],"value":[36],"exactly":[38],"minterm":[40,193],"from":[41,220],"0":[42],"1":[44,46],"or":[45,228],"0.":[48],"We":[49,88,187],"would":[50],"like":[51],"transform":[53],"I":[54],"into":[55],"I'":[56,62],"such":[58],"way":[60],"that":[61,91,191],"equivalent":[64,123,164],"This":[67],"sort":[70],"of":[71,99,140,148,169,223],"basic":[72],"operations":[73],"synthesis,":[77],"as":[78,159,236],"functional":[80],"changes":[81,194,205],"are":[82,212,234],"minimal":[83],"(only":[84],"minterm).":[87],"experimentally":[89,189],"show":[90,190],"even":[92],"if":[93,133],"change":[95,137,155],"functions":[96],"all":[98,127,207],"gates":[101],"circuit,":[104,150],"without":[106],"their":[108],"input":[109,157],"signals":[110,158],"(their":[111],"immediate":[112],"fanins),":[113],"i.e.,":[114],"no":[115],"topological":[116],"changes,":[117],"can":[120],"never":[121],"become":[122],"cases":[129,171],"tried.":[131],"However,":[132],"allow":[135,153],"function":[139],"gate":[143,182],"last":[146,185],"level":[147],"well,":[160],"becomes":[163],"around":[167],"13%":[168],"average":[173,176],"with":[174,200],"additional":[177],"1.1":[178],"inputs":[179],"level.":[186],"also":[188],"tables":[197],"are,":[198],"comparing":[199],"two":[203],"products":[204,211],"where":[206],"minterms":[208],"inside":[209],"changed,":[213],"most":[215],"difficult":[216],"problems":[217],"accommodate":[219],"viewpoint":[222],"Engineering":[224],"Change":[225],"Order":[226],"(ECO)":[227],"debugging,":[230],"when":[231],"circuits":[233],"implemented":[235],"logic.":[238]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}