{"id":"https://openalex.org/W2550608975","doi":"https://doi.org/10.1109/hldvt.2016.7748267","title":"Clock domain crossing formal verification: a meta-model","display_name":"Clock domain crossing formal verification: a meta-model","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2550608975","doi":"https://doi.org/10.1109/hldvt.2016.7748267","mag":"2550608975"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2016.7748267","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2016.7748267","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039969801","display_name":"Mejid Kebaili","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I4210124177","display_name":"STMicroelectronics (Czechia)","ror":"https://ror.org/03c7ss521","country_code":"CZ","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210124177"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["CZ","FR"],"is_corresponding":true,"raw_author_name":"Mejid Kebaili","raw_affiliation_strings":["STMicroelectronics","Univ. Grenoble Alpes and CNRS, TIMA Laboratory, Grenoble"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics","institution_ids":["https://openalex.org/I4210124177"]},{"raw_affiliation_string":"Univ. Grenoble Alpes and CNRS, TIMA Laboratory, Grenoble","institution_ids":["https://openalex.org/I4210087012","https://openalex.org/I1294671590","https://openalex.org/I899635006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069426138","display_name":"Jean-Christophe Brignone","orcid":null},"institutions":[{"id":"https://openalex.org/I4210124177","display_name":"STMicroelectronics (Czechia)","ror":"https://ror.org/03c7ss521","country_code":"CZ","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210124177"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Jean-christophe Brignone","raw_affiliation_strings":["STMicroelectronics"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics","institution_ids":["https://openalex.org/I4210124177"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067330751","display_name":"Katell Morin-Allory","orcid":null},"institutions":[{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Katell Morin-Allory","raw_affiliation_strings":["Univ. Grenoble Alpes and CNRS, TIMA Laboratory, Grenoble"],"affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes and CNRS, TIMA Laboratory, Grenoble","institution_ids":["https://openalex.org/I4210087012","https://openalex.org/I1294671590","https://openalex.org/I899635006"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5039969801"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210124177","https://openalex.org/I899635006"],"apc_list":null,"apc_paid":null,"fwci":0.3153,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.59309761,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"136","last_page":"141"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.9841755032539368},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7776872515678406},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7747030258178711},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5625830292701721},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5353778600692749},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.44568055868148804},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.43823081254959106},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4321242570877075},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4314417243003845},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.43134886026382446},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.42394471168518066},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.418715238571167},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3547552227973938},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3031178414821625},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.2939116656780243},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2937300503253937},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23602938652038574},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.2112572193145752},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11369022727012634}],"concepts":[{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.9841755032539368},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7776872515678406},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7747030258178711},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5625830292701721},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5353778600692749},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.44568055868148804},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.43823081254959106},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4321242570877075},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4314417243003845},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.43134886026382446},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.42394471168518066},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.418715238571167},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3547552227973938},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3031178414821625},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2939116656780243},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2937300503253937},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23602938652038574},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.2112572193145752},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11369022727012634},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2016.7748267","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2016.7748267","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6000000238418579,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320719","display_name":"Department of Science and Technology, Ministry of Science and Technology, India","ror":"https://ror.org/0101xrq71"},{"id":"https://openalex.org/F4320332162","display_name":"Centers for Disease Control and Prevention","ror":"https://ror.org/042twtr12"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1520384708","https://openalex.org/W1969939389","https://openalex.org/W1996072625","https://openalex.org/W2036982823","https://openalex.org/W2052006175","https://openalex.org/W2062147277","https://openalex.org/W2066746455","https://openalex.org/W2077526014","https://openalex.org/W2119616711","https://openalex.org/W2129981070","https://openalex.org/W3142972151","https://openalex.org/W3147673367","https://openalex.org/W4239411689","https://openalex.org/W4250693127"],"related_works":["https://openalex.org/W853533475","https://openalex.org/W628161287","https://openalex.org/W2095703739","https://openalex.org/W2477469844","https://openalex.org/W2187779671","https://openalex.org/W2325117947","https://openalex.org/W2377749234","https://openalex.org/W2108168368","https://openalex.org/W2349909378","https://openalex.org/W794031490"],"abstract_inverted_index":{"In":[0],"the":[1,71],"context":[2],"of":[3,28,54,66],"industrial":[4],"designs,":[5],"circuits":[6],"are":[7],"based":[8,49],"on":[9,13,50],"many":[10],"IPs":[11],"defined":[12],"their":[14],"own":[15],"clock":[16,31],"domain.":[17],"It":[18],"leads":[19],"to":[20,37],"globally":[21],"asynchronous":[22],"locally":[23],"synchronous":[24],"designs.":[25],"The":[26],"transmission":[27],"data":[29,42],"between":[30],"domains":[32],"must":[33],"be":[34],"carefully":[35],"verified":[36],"avoid":[38],"metastability,":[39],"inconsistency":[40],"and":[41,73],"loss.":[43],"EDA":[44],"tools":[45],"propose":[46,63],"a":[47,51,55,64],"strategy":[48],"minimal":[52],"detection":[53],"synchronizer":[56,67],"structure.":[57],"Conversely,":[58],"in":[59],"this":[60],"paper":[61],"we":[62],"meta-model":[65],"that":[68],"speeds":[69],"up":[70],"proof":[72],"ensures":[74],"its":[75],"better":[76],"automation.":[77]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}