{"id":"https://openalex.org/W2032952398","doi":"https://doi.org/10.1109/hldvt.2012.6418244","title":"A functional test generation technique for RTL datapaths","display_name":"A functional test generation technique for RTL datapaths","publication_year":2012,"publication_date":"2012-11-01","ids":{"openalex":"https://openalex.org/W2032952398","doi":"https://doi.org/10.1109/hldvt.2012.6418244","mag":"2032952398"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2012.6418244","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2012.6418244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069623023","display_name":"Bijan Alizadeh","orcid":"https://orcid.org/0000-0003-4436-4597"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Bijan Alizadeh","raw_affiliation_strings":["School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), CREST, University of Tokyo, Japan","VLSI Design and Education Center (VDEC), University of Tokyo and CREST, Japan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), CREST, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo and CREST, Japan#TAB#","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"64","last_page":"70"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.909420907497406},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9027619361877441},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6763487458229065},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.644059419631958},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5784795880317688},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5117937922477722},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.48108622431755066},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.46327897906303406},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43560701608657837},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.41793346405029297},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4153513014316559},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4101754426956177},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3509076237678528},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3473494350910187},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.323486328125},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.31877297163009644},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.23668283224105835},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.23292195796966553},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16915646195411682},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08345407247543335}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.909420907497406},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9027619361877441},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6763487458229065},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.644059419631958},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5784795880317688},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5117937922477722},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.48108622431755066},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.46327897906303406},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43560701608657837},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.41793346405029297},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4153513014316559},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4101754426956177},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3509076237678528},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3473494350910187},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.323486328125},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.31877297163009644},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.23668283224105835},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.23292195796966553},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16915646195411682},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08345407247543335},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2012.6418244","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2012.6418244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2004917085","https://openalex.org/W2013634896","https://openalex.org/W2073306964","https://openalex.org/W2115180022","https://openalex.org/W2119713856","https://openalex.org/W2127005882","https://openalex.org/W2140546147","https://openalex.org/W2157602480","https://openalex.org/W2158966008","https://openalex.org/W2162406453","https://openalex.org/W2171399778","https://openalex.org/W3144091741","https://openalex.org/W4234489476","https://openalex.org/W4234537939","https://openalex.org/W6651313382","https://openalex.org/W6683308379"],"related_works":["https://openalex.org/W2117563988","https://openalex.org/W2091833418","https://openalex.org/W1412895167","https://openalex.org/W2120257283","https://openalex.org/W2913077774","https://openalex.org/W4256030018","https://openalex.org/W2145089576","https://openalex.org/W2543176856","https://openalex.org/W1493811107","https://openalex.org/W2624668974"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"automatic":[4],"test":[5],"pattern":[6],"generation":[7],"(ATPG)":[8],"technique":[9],"applicable":[10],"to":[11,24,32,40,67,76,92],"register":[12],"transfer":[13],"level":[14],"(RTL)":[15],"datapath":[16],"circuits":[17],"which":[18,56],"are":[19],"usually":[20],"very":[21],"hard-to-test":[22],"due":[23],"the":[25,64,72,93,100,111],"presence":[26],"of":[27,59,74,88],"complex":[28],"loop":[29],"structures.":[30],"Although":[31],"achieve":[33],"high":[34],"fault":[35],"coverage":[36],"it":[37],"is":[38,79],"essential":[39],"symbolically":[41],"simulate":[42],"all":[43],"possible":[44],"execution":[45],"paths,":[46],"we":[47],"have":[48],"come":[49],"up":[50],"with":[51,106,108],"a":[52],"case":[53,109],"splitting":[54,110],"mechanism":[55],"makes":[57],"use":[58],"path":[60],"sensitization":[61],"information":[62],"from":[63],"faulty":[65],"location":[66],"primary":[68],"outputs":[69],"so":[70],"that":[71],"size":[73],"formulae":[75],"be":[77],"solved":[78],"significantly":[80],"reduced.":[81],"Experimental":[82],"results":[83,101],"show":[84],"robustness":[85],"and":[86],"reliability":[87],"our":[89],"method":[90],"compared":[91],"state-of-the-art":[94],"RTL":[95],"ATPG":[96,112],"techniques.":[97],"In":[98],"addition,":[99],"indicate":[102],"that,":[103],"in":[104],"comparison":[105],"[8],":[107],"time":[113],"has":[114],"been":[115],"reduced":[116],"by":[117],"22%-41%.":[118]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}