{"id":"https://openalex.org/W2160293543","doi":"https://doi.org/10.1109/hldvt.2011.6114167","title":"IP-XACT based system level mutation testing","display_name":"IP-XACT based system level mutation testing","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W2160293543","doi":"https://doi.org/10.1109/hldvt.2011.6114167","mag":"2160293543"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2011.6114167","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2011.6114167","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International High Level Design Validation and Test Workshop","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048118068","display_name":"Tao Xie","orcid":"https://orcid.org/0000-0002-6731-216X"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Tao Xie","raw_affiliation_strings":["C-LAB, University of Paderborn, Paderborn, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"C-LAB, University of Paderborn, Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110622459","display_name":"Wolfgang M\u00fcller","orcid":"https://orcid.org/0000-0001-6474-3733"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Mueller","raw_affiliation_strings":["C-LAB, University of Paderborn, Paderborn, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"C-LAB, University of Paderborn, Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054892568","display_name":"Florian Letombe","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Florian Letombe","raw_affiliation_strings":["SpringSoft Inc., Moirans, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SpringSoft Inc., Moirans, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048118068"],"corresponding_institution_ids":["https://openalex.org/I206945453"],"apc_list":null,"apc_paid":null,"fwci":1.6206,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.85897674,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"65","last_page":"71"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7740570902824402},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5010521411895752},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.43577465415000916},{"id":"https://openalex.org/keywords/xml","display_name":"XML","score":0.4304477572441101},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.4168163537979126},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34069764614105225},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33229389786720276},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18126177787780762},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1306573450565338}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7740570902824402},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5010521411895752},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.43577465415000916},{"id":"https://openalex.org/C8797682","wikidata":"https://www.wikidata.org/wiki/Q2115","display_name":"XML","level":2,"score":0.4304477572441101},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.4168163537979126},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34069764614105225},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33229389786720276},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18126177787780762},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1306573450565338},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2011.6114167","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2011.6114167","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International High Level Design Validation and Test Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W34866348","https://openalex.org/W146458024","https://openalex.org/W1527465803","https://openalex.org/W1989065170","https://openalex.org/W2011848140","https://openalex.org/W2049695835","https://openalex.org/W2066644134","https://openalex.org/W2102844362","https://openalex.org/W2103825248","https://openalex.org/W2114431978","https://openalex.org/W2120552859","https://openalex.org/W2123329891","https://openalex.org/W2131729621","https://openalex.org/W2150764159","https://openalex.org/W2153824114","https://openalex.org/W2154809971","https://openalex.org/W2157755550","https://openalex.org/W2165310406","https://openalex.org/W2168383855","https://openalex.org/W3145296564","https://openalex.org/W3149907469","https://openalex.org/W4232177410","https://openalex.org/W4243707100","https://openalex.org/W4251716291","https://openalex.org/W6684534873"],"related_works":["https://openalex.org/W3142211975","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2944867581","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W4292904049","https://openalex.org/W2136848245","https://openalex.org/W1978899622","https://openalex.org/W4213404769"],"abstract_inverted_index":{"Mutation-testing":[0],"has":[1,27],"been":[2],"considered":[3],"as":[4,77],"an":[5,92,120,171,207],"important":[6],"coverage":[7,59],"metric":[8,60],"to":[9,29,54,218],"measure":[10],"the":[11,23,30,56,126,134,150,156,164,176,196,202,220,223],"quality":[12],"of":[13,136,160,178,215,222],"simulation-based":[14],"verification":[15],"and":[16,36,45,118,158,167],"validation":[17],"processes":[18],"[1,":[19],"2,":[20],"3].":[21],"On":[22],"other":[24],"hand,":[25],"IP-XACT":[26,78,96,110,121,130,143,173,204],"evolved":[28],"IEEE":[31],"standard":[32],"for":[33,61,73,88,95,191,210],"IP":[34,64],"reuse":[35],"IP-based":[37],"System-on-Chip":[38],"(SoC)":[39],"integration,":[40],"which":[41,84,132],"covers":[42],"both":[43],"RTL":[44],"TLM.":[46],"In":[47],"this":[48,74],"paper,":[49],"we":[50,90,100,115,124,139,198],"present":[51],"our":[52],"effort":[53],"enable":[55],"mutation-based":[57],"simulation":[58,211],"system":[62,79],"level":[63],"integration":[65,157],"with":[66,175],"IP-XACT.":[67],"Two":[68],"major":[69],"ingredients":[70],"are":[71,81,85],"required":[72],"extension.":[75],"First,":[76],"designs":[80,144],"XML":[82,111],"files,":[83],"not":[86],"originally":[87],"execution,":[89],"need":[91],"execution/simulation":[93],"engine":[94],"designs.":[97],"For":[98],"this,":[99],"created":[101],"a":[102,153,188],"code":[103,165],"generator":[104,166],"that":[105,114,138,201],"generates":[106],"SystemC":[107],"models":[108],"from":[109],"designs,":[112],"such":[113],"can":[116,140,199],"simulate":[117],"test":[119],"design.":[122],"Second,":[123],"define":[125],"mutation":[127,146,151,168,205],"operators":[128,169],"on":[129,155,187],"schema,":[131],"is":[133],"model":[135],"errors":[137],"inject":[141],"into":[142],"during":[145],"testing.":[147],"With":[148],"IP-XACT,":[149],"maintains":[152],"focus":[154],"configuration":[159],"components.":[161],"We":[162],"implemented":[163],"in":[170,213],"Eclipsed-based":[172],"editor":[174],"help":[177],"Eclipse":[179],"Modeling":[180],"Framework.":[181],"Then":[182],"several":[183],"experiments":[184],"were":[185],"conducted":[186],"TLM":[189],"library":[190],"CoreConnect":[192],"SoC":[193],"modeling.":[194],"From":[195],"results,":[197],"see":[200],"defined":[203],"serves":[206],"effective":[208],"qualification":[209],"tests,":[212],"terms":[214],"its":[216],"ability":[217],"reveal":[219],"weakness":[221],"tests.":[224]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-29T09:16:38.111599","created_date":"2025-10-10T00:00:00"}