{"id":"https://openalex.org/W1982709980","doi":"https://doi.org/10.1109/hldvt.2010.5496655","title":"Automatic generation of host-compiled timed TLMs for high level design","display_name":"Automatic generation of host-compiled timed TLMs for high level design","publication_year":2010,"publication_date":"2010-06-01","ids":{"openalex":"https://openalex.org/W1982709980","doi":"https://doi.org/10.1109/hldvt.2010.5496655","mag":"1982709980"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2010.5496655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2010.5496655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109251050","display_name":"Samar Abdi","orcid":null},"institutions":[{"id":"https://openalex.org/I60158472","display_name":"Concordia University","ror":"https://ror.org/0420zvk78","country_code":"CA","type":"education","lineage":["https://openalex.org/I60158472"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Samar Abdi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Concordia University Montreal, Canada","[Department of Electrical and Computer Engineering, Concordia University, Montr\u00e9al, Canada]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Concordia University Montreal, Canada","institution_ids":["https://openalex.org/I60158472"]},{"raw_affiliation_string":"[Department of Electrical and Computer Engineering, Concordia University, Montr\u00e9al, Canada]","institution_ids":["https://openalex.org/I60158472"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5109251050"],"corresponding_institution_ids":["https://openalex.org/I60158472"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.06818397,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"103","last_page":"104"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.933100700378418},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8368678092956543},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.7017192840576172},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.6635838150978088},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5177880525588989},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5154167413711548},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4714958071708679},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45375654101371765},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4335516393184662},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.43129363656044006},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.43002814054489136},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37247756123542786},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2687496840953827},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.1606345772743225},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14628472924232483}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.933100700378418},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8368678092956543},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.7017192840576172},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.6635838150978088},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5177880525588989},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5154167413711548},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4714958071708679},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45375654101371765},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4335516393184662},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.43129363656044006},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.43002814054489136},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37247756123542786},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2687496840953827},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.1606345772743225},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14628472924232483},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2010.5496655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2010.5496655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.46000000834465027,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332688","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1814926891","https://openalex.org/W2104225326","https://openalex.org/W2112502086","https://openalex.org/W2114084469","https://openalex.org/W2117539868","https://openalex.org/W2121864144","https://openalex.org/W2124536457","https://openalex.org/W2139354295","https://openalex.org/W2155867784","https://openalex.org/W6677959934"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W2266880325","https://openalex.org/W2097331811","https://openalex.org/W2112120387","https://openalex.org/W1981924702","https://openalex.org/W2532163536","https://openalex.org/W3146089259","https://openalex.org/W4255608508"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,59],"case":[4],"for":[5,13,92],"using":[6],"automatically":[7],"generated":[8],"transaction":[9],"level":[10,15],"models":[11],"(TLMs)":[12],"high":[14],"design.":[16],"The":[17,52,71],"inputs":[18],"to":[19,28,67,103,108,131],"automatic":[20],"TLM":[21,72],"generation":[22],"are":[23,45],"application":[24],"C":[25,43,54],"tasks":[26,44],"mapped":[27],"processing":[29],"units":[30],"in":[31,41,105],"the":[32,36,38,42,63,69,79],"platform.":[33],"Based":[34],"on":[35,78],"mapping,":[37],"basic":[39],"blocks":[40],"analyzed":[46],"and":[47,75,116],"annotated":[48],"with":[49,58],"estimated":[50],"delays.":[51],"delay-annotated":[53],"code":[55],"is":[56,73],"linked":[57],"SystemC":[60],"model":[61],"of":[62,111,119],"platform's":[64],"communication":[65],"architecture":[66],"generate":[68],"TLM.":[70],"compiled":[74],"executed":[76],"natively":[77],"host":[80],"machine,":[81],"making":[82],"it":[83],"much":[84],"faster":[85],"than":[86,134],"conventional":[87],"cycle":[88],"accurate":[89],"models.":[90],"TLMs":[91],"industrial":[93],"scale":[94],"designs":[95],"such":[96],"as":[97],"MP3":[98],"decoder":[99],"have":[100],"been":[101,129],"shown":[102,130],"simulate":[104],"seconds,":[106],"compared":[107],"3-4":[109],"hrs":[110,118],"instruction":[112],"set":[113],"simulation":[114,127],"(ISS)":[115],"15-18":[117],"RTL":[120],"simulation.":[121],"Timing":[122],"estimation":[123],"error":[124],"over":[125],"board":[126],"has":[128],"be":[132],"less":[133],"15%.":[135]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}