{"id":"https://openalex.org/W2002682434","doi":"https://doi.org/10.1109/hldvt.2010.5496646","title":"ESL design and multi-core validation using the System-on-Chip Environment","display_name":"ESL design and multi-core validation using the System-on-Chip Environment","publication_year":2010,"publication_date":"2010-06-01","ids":{"openalex":"https://openalex.org/W2002682434","doi":"https://doi.org/10.1109/hldvt.2010.5496646","mag":"2002682434"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2010.5496646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2010.5496646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100367140","display_name":"Weiwei Chen","orcid":"https://orcid.org/0000-0003-2845-1666"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Weiwei Chen","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, USA","[Center for Embedded Computer Systems University of California, Irvine, USA]"],"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"[Center for Embedded Computer Systems University of California, Irvine, USA]","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101786912","display_name":"Xu Han","orcid":"https://orcid.org/0000-0003-0068-0117"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xu Han","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, USA","[Center for Embedded Computer Systems University of California, Irvine, USA]"],"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"[Center for Embedded Computer Systems University of California, Irvine, USA]","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111950361","display_name":"Rainer D\u00f6mer","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rainer Domer","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, USA","[Center for Embedded Computer Systems University of California, Irvine, USA]"],"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"[Center for Embedded Computer Systems University of California, Irvine, USA]","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100367140"],"corresponding_institution_ids":["https://openalex.org/I204250578"],"apc_list":null,"apc_paid":null,"fwci":1.2484,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80264045,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"4","issue":null,"first_page":"142","last_page":"147"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9747829437255859},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7988477945327759},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.727813184261322},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6961711645126343},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6160932779312134},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5729983448982239},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.5186768770217896},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.4724852442741394},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4598484933376312},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4469112157821655},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.44459444284439087},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1860537827014923},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.173717200756073}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9747829437255859},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7988477945327759},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.727813184261322},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6961711645126343},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6160932779312134},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5729983448982239},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.5186768770217896},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.4724852442741394},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4598484933376312},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4469112157821655},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.44459444284439087},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1860537827014923},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.173717200756073},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2010.5496646","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2010.5496646","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320324004","display_name":"Forskningsr\u00e5det om H\u00e4lsa, Arbetsliv och V\u00e4lf\u00e4rd","ror":"https://ror.org/02d290r06"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W87720826","https://openalex.org/W1496267491","https://openalex.org/W1498455513","https://openalex.org/W1574383382","https://openalex.org/W1606313114","https://openalex.org/W1608473921","https://openalex.org/W2045196269","https://openalex.org/W2059308604","https://openalex.org/W2073906129","https://openalex.org/W2094920868","https://openalex.org/W2100512555","https://openalex.org/W2106219841","https://openalex.org/W2138612658","https://openalex.org/W2142992647","https://openalex.org/W2146897346","https://openalex.org/W2148548948","https://openalex.org/W2150408604","https://openalex.org/W2154100842","https://openalex.org/W2274065588","https://openalex.org/W2503657378","https://openalex.org/W4238966373","https://openalex.org/W6629762304","https://openalex.org/W6636530238"],"related_works":["https://openalex.org/W2169248084","https://openalex.org/W1973069902","https://openalex.org/W2116793508","https://openalex.org/W53262038","https://openalex.org/W2133408453","https://openalex.org/W2002682434","https://openalex.org/W2016843712","https://openalex.org/W2545414197","https://openalex.org/W4230718388","https://openalex.org/W2117995643"],"abstract_inverted_index":{"Design":[0],"at":[1,25],"the":[2,7,15,41,62,90,101,119,122],"Electronic":[3],"System-Level":[4],"(ESL)":[5],"tackles":[6],"increasing":[8],"complexity":[9],"of":[10,17,61,100,113,121],"embedded":[11],"systems":[12],"by":[13],"raising":[14],"level":[16],"abstraction":[18],"in":[19,37],"system":[20],"specification":[21],"and":[22,39],"modeling.":[23],"Aiming":[24],"an":[26,59],"automated":[27],"top-down":[28,84],"synthesis":[29],"flow,":[30,93],"effective":[31,80],"ESL":[32,68],"design":[33,43,86,92],"frameworks":[34],"are":[35],"needed":[36],"transforming":[38],"refining":[40],"highlevel":[42],"models":[44],"until":[45],"a":[46,66,126,130],"satisfactory":[47],"multi-processor":[48],"system-on-chip":[49],"(MPSoC)":[50],"implementation":[51],"is":[52],"reached.":[53],"In":[54],"this":[55,94],"paper,":[56],"we":[57],"provide":[58],"overview":[60],"System-on-Chip":[63],"Environment":[64],"(SCE),":[65],"SpecC-based":[67],"framework":[69,76],"for":[70,81,110],"heterogeneous":[71],"MPSoC":[72,115],"design.":[73],"Our":[74],"SCE":[75,91,102],"has":[77],"been":[78],"shown":[79],"its":[82],"designer-controlled":[83],"refinement-based":[85],"methodology.":[87],"After":[88],"reviewing":[89],"paper":[95],"highlights":[96],"our":[97],"recent":[98],"extension":[99],"simulation":[103,109,124],"engine":[104],"to":[105],"support":[106],"multi-core":[107],"parallel":[108,123],"fast":[111],"validation":[112],"large":[114],"designs.":[116],"We":[117],"demonstrate":[118],"benefits":[120],"using":[125],"case":[127],"study":[128],"on":[129],"H.264":[131],"video":[132],"decoder":[133],"application.":[134]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}