{"id":"https://openalex.org/W2134885745","doi":"https://doi.org/10.1109/hldvt.2009.5340181","title":"MCBCG: Model Checking Based Sequential Clock-Gating","display_name":"MCBCG: Model Checking Based Sequential Clock-Gating","publication_year":2009,"publication_date":"2009-11-01","ids":{"openalex":"https://openalex.org/W2134885745","doi":"https://doi.org/10.1109/hldvt.2009.5340181","mag":"2134885745"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2009.5340181","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2009.5340181","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International High Level Design Validation and Test Workshop","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005028151","display_name":"Sumit Ahuja","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sumit Ahuja","raw_affiliation_strings":["CESCA, Virginia Technology, Blacksburg, VA, USA","CESCA, Virginia Tech, Blacksburg, 24061, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CESCA, Virginia Technology, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"CESCA, Virginia Tech, Blacksburg, 24061, USA#TAB#","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021517996","display_name":"Sandeep K. Shukla","orcid":"https://orcid.org/0000-0001-5525-7426"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandeep Shukla","raw_affiliation_strings":["CESCA, Virginia Technology, Blacksburg, VA, USA","CESCA, Virginia Tech, Blacksburg, 24061, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CESCA, Virginia Technology, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"CESCA, Virginia Tech, Blacksburg, 24061, USA#TAB#","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":2.9125,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.91237076,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"20","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9918000102043152,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.8543481230735779},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8013792037963867},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.6551194787025452},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.499340295791626},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4636491537094116},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.4468711316585541},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.4187832772731781},{"id":"https://openalex.org/keywords/a-priori-and-a-posteriori","display_name":"A priori and a posteriori","score":0.41335782408714294},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3704782724380493},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3478624224662781},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.3201924264431},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31885746121406555},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22380521893501282},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11114361882209778},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.10539132356643677},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07627755403518677}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.8543481230735779},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8013792037963867},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.6551194787025452},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.499340295791626},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4636491537094116},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.4468711316585541},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.4187832772731781},{"id":"https://openalex.org/C75553542","wikidata":"https://www.wikidata.org/wiki/Q178161","display_name":"A priori and a posteriori","level":2,"score":0.41335782408714294},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3704782724380493},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3478624224662781},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.3201924264431},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31885746121406555},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22380521893501282},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11114361882209778},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.10539132356643677},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07627755403518677},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2009.5340181","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2009.5340181","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International High Level Design Validation and Test Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7900000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1492580319","https://openalex.org/W1596716095","https://openalex.org/W1992328013","https://openalex.org/W2102488630","https://openalex.org/W2135183949","https://openalex.org/W2161537396","https://openalex.org/W2164050549","https://openalex.org/W4234129059","https://openalex.org/W4245631385","https://openalex.org/W6648313114"],"related_works":["https://openalex.org/W2559451387","https://openalex.org/W1999924508","https://openalex.org/W2061180121","https://openalex.org/W4247180033","https://openalex.org/W2088914741","https://openalex.org/W2040807843","https://openalex.org/W2117814846","https://openalex.org/W2259094912","https://openalex.org/W2546524276","https://openalex.org/W4249038728"],"abstract_inverted_index":{"Dynamic":[0],"power":[1,160],"reduction":[2,161],"techniques":[3],"such":[4,54,86,127],"as":[5,87],"sequential":[6,19,38,48,58,77,115],"clock-gating":[7,20,78,158],"aim":[8],"at":[9],"eliminating":[10],"inconsequential":[11],"computation":[12],"and":[13,63,83,90,122],"clock-toggles":[14],"of":[15,29,37,45,76,117],"the":[16,43,46,74,96,101,155],"registers.":[17],"Usually":[18],"opportunities":[21,79],"are":[22,61],"discovered":[23],"manually":[24],"based":[25,64,159],"on":[26,65,119],"certain":[27],"characteristics":[28],"a":[30,92],"design":[31],"(e.g.":[32],"pipelining).":[33],"Since":[34],"manual":[35],"addition":[36],"gating":[39,126],"circuitry":[40],"might":[41],"change":[42],"functionality":[44],"design,":[47],"equivalence":[49,59],"checking":[50,60,89],"is":[51,70,140],"needed":[52],"after":[53],"changes.":[55],"Tools":[56],"for":[57,137],"expensive,":[62],"recent":[66],"technologies.":[67],"Therefore,":[68],"it":[69],"desirable":[71],"to":[72,150],"automate":[73],"discovery":[75],"using":[80],"already":[81],"existing":[82],"proven":[84],"technologies":[85],"model":[88],"thereby":[91],"priori":[93],"proving":[94],"that":[95],"changes":[97],"will":[98,129],"not":[99,130],"affect":[100],"required":[102],"functionality.":[103],"Model":[104],"Checking":[105],"Based":[106],"Sequential":[107],"Clock":[108],"Gating":[109],"(MCBCG)":[110],"method":[111],"formally":[112],"proves":[113],"particular":[114],"dependencies":[116],"registers":[118,121,128],"other":[120],"logic,":[123],"thus":[124],"sequentially":[125],"require":[131],"further":[132],"validation.":[133],"An":[134],"automation":[135],"scheme":[136],"MCBCG":[138],"methodology":[139],"also":[141],"proposed":[142],"in":[143],"this":[144],"paper.":[145],"Preliminary":[146],"experiments":[147],"show":[148],"up":[149],"30%":[151],"more":[152],"savings":[153],"than":[154],"traditional":[156],"(combinational)":[157],"techniques.":[162]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}