{"id":"https://openalex.org/W2125634733","doi":"https://doi.org/10.1109/hldvt.2008.4695881","title":"Test and validation of a non-deterministic system &amp;#x2014; True Random Number Generator","display_name":"Test and validation of a non-deterministic system &amp;#x2014; True Random Number Generator","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2125634733","doi":"https://doi.org/10.1109/hldvt.2008.4695881","mag":"2125634733"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2008.4695881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2008.4695881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International High Level Design Validation and Test Workshop","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078653246","display_name":"Kapila Udawatta","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":true,"raw_author_name":"Kapila Udawatta","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101910168","display_name":"Mehdi Ehsanian","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Mehdi Ehsanian","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025594118","display_name":"Sergey Maidanov","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Sergey Maidanov","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027579229","display_name":"S. Musunuri","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Surya Musunuri","raw_affiliation_strings":["Intel Corporation","Intel Corp., USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Intel Corp., USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5078653246"],"corresponding_institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.10704269,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2523","issue":null,"first_page":"77","last_page":"84"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9864000082015991,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9821000099182129,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nist","display_name":"NIST","score":0.847527265548706},{"id":"https://openalex.org/keywords/random-number-generation","display_name":"Random number generation","score":0.7238763570785522},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7141086459159851},{"id":"https://openalex.org/keywords/chipset","display_name":"Chipset","score":0.5938917398452759},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.5425070524215698},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5337252616882324},{"id":"https://openalex.org/keywords/statistical-hypothesis-testing","display_name":"Statistical hypothesis testing","score":0.4765625298023224},{"id":"https://openalex.org/keywords/system-testing","display_name":"System testing","score":0.4111191928386688},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22637119889259338},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16478458046913147},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.12120658159255981},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12037160992622375},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.11455529928207397},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.09006717801094055}],"concepts":[{"id":"https://openalex.org/C111219384","wikidata":"https://www.wikidata.org/wiki/Q6954384","display_name":"NIST","level":2,"score":0.847527265548706},{"id":"https://openalex.org/C201866948","wikidata":"https://www.wikidata.org/wiki/Q228206","display_name":"Random number generation","level":2,"score":0.7238763570785522},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7141086459159851},{"id":"https://openalex.org/C73431340","wikidata":"https://www.wikidata.org/wiki/Q182656","display_name":"Chipset","level":3,"score":0.5938917398452759},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5425070524215698},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5337252616882324},{"id":"https://openalex.org/C87007009","wikidata":"https://www.wikidata.org/wiki/Q210832","display_name":"Statistical hypothesis testing","level":2,"score":0.4765625298023224},{"id":"https://openalex.org/C7166840","wikidata":"https://www.wikidata.org/wiki/Q1199682","display_name":"System testing","level":2,"score":0.4111191928386688},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22637119889259338},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16478458046913147},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.12120658159255981},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12037160992622375},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.11455529928207397},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.09006717801094055},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C204321447","wikidata":"https://www.wikidata.org/wiki/Q30642","display_name":"Natural language processing","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2008.4695881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2008.4695881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International High Level Design Validation and Test Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1568780897","https://openalex.org/W2075556783","https://openalex.org/W2107217398","https://openalex.org/W2111877940","https://openalex.org/W2177571745","https://openalex.org/W3151438815"],"related_works":["https://openalex.org/W2158491338","https://openalex.org/W2807901368","https://openalex.org/W2361454123","https://openalex.org/W2133733652","https://openalex.org/W2385247776","https://openalex.org/W2127916158","https://openalex.org/W2100196563","https://openalex.org/W2072658171","https://openalex.org/W2606392311","https://openalex.org/W2106546050"],"abstract_inverted_index":{"We":[0,91],"present":[1,31,92],"a":[2,8,12,55,93,101,112],"validation":[3,77],"and":[4,28,50,69,76],"test":[5],"methodology":[6,37,96,122],"for":[7,97],"non-deterministic":[9,131],"system,":[10],"namely":[11],"True":[13],"Random":[14],"Number":[15],"Generator":[16],"(TRNG).":[17],"The":[18],"TRNG":[19,56,74,98,115],"testing":[20,53,75,99,111,128],"methods":[21],"at":[22],"Intel":[23],"have":[24],"matured":[25],"over":[26],"time,":[27],"what":[29],"we":[30],"here":[32],"is":[33],"the":[34,73,127],"3rd":[35],"generation":[36],"used":[38],"in":[39,79,87,100],"our":[40],"latest":[41],"chipset":[42],"products.":[43],"In":[44],"addition":[45],"to":[46,61,117,126],"well":[47],"known":[48],"DFT":[49],"DFV":[51],"techniques,":[52],"of":[54,129],"requires":[57],"rigorous":[58],"statistical":[59,95],"analysis":[60],"determine":[62],"its":[63],"proper":[64],"operation.":[65],"Known":[66],"published":[67],"works":[68],"standards":[70],"donpsilat":[71],"address":[72],"issues":[78],"high":[80,102],"volumes":[81],"or":[82],"their":[83],"recommendations":[84],"are":[85],"impractical":[86],"real":[88],"manufacturing":[89,104],"constraints.":[90],"practical":[94],"volume":[103],"environment.":[105],"Its":[106],"validity":[107],"was":[108],"proven":[109],"by":[110],"65-nm":[113],"CMOS-based":[114],"design":[116],"meet":[118],"NIST":[119],"standards.":[120],"Our":[121],"can":[123],"be":[124],"extended":[125],"similar":[130],"systems.":[132]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
