{"id":"https://openalex.org/W4232787507","doi":"https://doi.org/10.1109/hldvt.2005.1568826","title":"Validating families of latency insensitive protocols","display_name":"Validating families of latency insensitive protocols","publication_year":2006,"publication_date":"2006-01-18","ids":{"openalex":"https://openalex.org/W4232787507","doi":"https://doi.org/10.1109/hldvt.2005.1568826"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2005.1568826","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2005.1568826","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034451736","display_name":"S. Suhaib","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Suhaib","raw_affiliation_strings":["Fermat Laboratory, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Fermat Laboratory, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018008542","display_name":"D. Mathaikutty","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Mathaikutty","raw_affiliation_strings":["Fermat Laboratory, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Fermat Laboratory, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111280296","display_name":"Shreyashi Shukla","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Shukla","raw_affiliation_strings":["Fermat Laboratory, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Fermat Laboratory, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056066445","display_name":"D. Berner","orcid":null},"institutions":[{"id":"https://openalex.org/I2802519937","display_name":"Institut de Recherche en Informatique et Syst\u00e8mes Al\u00e9atoires","ror":"https://ror.org/00myn0z94","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I2802519937","https://openalex.org/I28221208","https://openalex.org/I4210127572","https://openalex.org/I4210159245","https://openalex.org/I56067802"]},{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en sciences et technologies du num\u00e9rique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"government","lineage":["https://openalex.org/I1326498283"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"D. Berner","raw_affiliation_strings":["INRIA-IRISA, Campus Universitaire de Beaulieu, Rennes, France"],"affiliations":[{"raw_affiliation_string":"INRIA-IRISA, Campus Universitaire de Beaulieu, Rennes, France","institution_ids":["https://openalex.org/I2802519937","https://openalex.org/I1326498283"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5034451736"],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":0.5575,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.7026798,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"127","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.9286118149757385},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8367619514465332},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6970047950744629},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6288368701934814},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6011978387832642},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.4461890459060669},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.419542521238327},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3810117244720459},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3657705783843994},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.34623923897743225},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.24431264400482178},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07022914290428162},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06820377707481384}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.9286118149757385},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8367619514465332},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6970047950744629},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6288368701934814},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6011978387832642},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.4461890459060669},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.419542521238327},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3810117244720459},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3657705783843994},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.34623923897743225},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24431264400482178},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07022914290428162},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06820377707481384},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2005.1568826","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2005.1568826","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W65795563","https://openalex.org/W1542768242","https://openalex.org/W1829244603","https://openalex.org/W1933035759","https://openalex.org/W1999823427","https://openalex.org/W2120062652","https://openalex.org/W2144148413","https://openalex.org/W2160566592","https://openalex.org/W2181601762","https://openalex.org/W4229823398","https://openalex.org/W4240110784","https://openalex.org/W4244400208","https://openalex.org/W6602591826","https://openalex.org/W6681131238","https://openalex.org/W6685653829"],"related_works":["https://openalex.org/W2111870610","https://openalex.org/W2152752131","https://openalex.org/W161255303","https://openalex.org/W1544097700","https://openalex.org/W1488573418","https://openalex.org/W1922520186","https://openalex.org/W1946493810","https://openalex.org/W2037121848","https://openalex.org/W2391979747","https://openalex.org/W2981877881"],"abstract_inverted_index":{"With":[0],"increasing":[1],"clock":[2,19],"frequencies,":[3],"the":[4,18,50,53,127],"signal":[5],"delay":[6],"on":[7,13],"some":[8],"interconnects":[9],"in":[10,126],"an":[11,59],"system":[12,30],"chip":[14],"(SoC)":[15],"often":[16],"exceeds":[17],"period,":[20],"which":[21],"necessitates":[22],"latency":[23,42],"insensitive":[24],"protocols":[25],"(LIPs).":[26],"Correctness":[27],"of":[28,32,49,90,101,118,129],"a":[29,45,123],"composed":[31],"synchronous":[33,47],"blocks":[34],"communicating":[35],"via":[36],"LIPs":[37,135],"is":[38,61],"established":[39],"by":[40],"showing":[41],"equivalence":[43],"between":[44],"completely":[46],"composition":[48],"blocks,":[51],"and":[52,68,82,112],"LIP":[54,60],"based":[55],"composition.":[56],"Every":[57],"time":[58],"conceived,":[62],"they":[63],"need":[64],"to":[65,74,84,132,137],"be":[66,122],"debugged":[67],"then":[69],"proven":[70],"correct.":[71],"Mathematical":[72],"theorems":[73],"establish":[75],"correctness,":[76],"though":[77],"elegant,":[78],"are":[79],"error":[80],"prone,":[81],"tedious":[83],"create":[85,133],"for":[86,99,104,108,115,141],"every":[87],"new":[88,134],"variant":[89],"LIPs.":[91],"In":[92],"this":[93],"work,":[94],"we":[95],"present":[96],"validation":[97],"frameworks":[98],"families":[100],"LIPs,":[102],"both":[103],"dynamic":[105],"validation,":[106],"useful":[107,124],"early":[109],"debug":[110],"cycles,":[111],"formal":[113,116],"verification":[114],"proof":[117],"correctness.":[119],"This":[120],"can":[121],"framework":[125],"hands":[128],"designers":[130],"trying":[131],"or":[136],"optimize":[138],"existing":[139],"ones":[140],"design":[142],"convergence.":[143]},"counts_by_year":[{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}