{"id":"https://openalex.org/W2160289783","doi":"https://doi.org/10.1109/hldvt.2005.1568818","title":"A software test program generator for verifying system-on-chips","display_name":"A software test program generator for verifying system-on-chips","publication_year":2006,"publication_date":"2006-01-18","ids":{"openalex":"https://openalex.org/W2160289783","doi":"https://doi.org/10.1109/hldvt.2005.1568818","mag":"2160289783"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2005.1568818","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2005.1568818","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110059612","display_name":"Andrew Cheng","orcid":null},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"A. Cheng","raw_affiliation_strings":["Freescale Semiconductor Australia Private Limited, Adelaide, SA, Australia","School of Electrical and Electronic Engineering, University of Adelaide, Adelaide, SA, Australia"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Australia Private Limited, Adelaide, SA, Australia","institution_ids":[]},{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University of Adelaide, Adelaide, SA, Australia","institution_ids":["https://openalex.org/I5681781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023255651","display_name":"Cheng\u2010Chew Lim","orcid":"https://orcid.org/0000-0002-2463-9760"},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Cheng-Chew Lim","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University of Adelaide, Adelaide, SA, Australia"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University of Adelaide, Adelaide, SA, Australia","institution_ids":["https://openalex.org/I5681781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045630735","display_name":"Atanas Parashkevov","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Parashkevov","raw_affiliation_strings":["Freescale Semiconductor Australia Private Limited, Adelaide, SA, Australia"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor Australia Private Limited, Adelaide, SA, Australia","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110059612"],"corresponding_institution_ids":["https://openalex.org/I5681781"],"apc_list":null,"apc_paid":null,"fwci":3.6236,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.93146912,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"79","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7256219983100891},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5985140800476074},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.568642258644104},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.5650467872619629},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4993014335632324},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.48677802085876465},{"id":"https://openalex.org/keywords/software-verification","display_name":"Software verification","score":0.4864666163921356},{"id":"https://openalex.org/keywords/verification-and-validation","display_name":"Verification and validation","score":0.4522257447242737},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.3424564301967621},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.3376256823539734},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.24545395374298096},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15011504292488098}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7256219983100891},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5985140800476074},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.568642258644104},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5650467872619629},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4993014335632324},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.48677802085876465},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.4864666163921356},{"id":"https://openalex.org/C48002344","wikidata":"https://www.wikidata.org/wiki/Q2919644","display_name":"Verification and validation","level":2,"score":0.4522257447242737},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.3424564301967621},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.3376256823539734},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24545395374298096},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15011504292488098},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/hldvt.2005.1568818","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2005.1568818","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:digital.library.adelaide.edu.au:2440/28565","is_oa":false,"landing_page_url":"http://hdl.handle.net/2440/28565","pdf_url":null,"source":{"id":"https://openalex.org/S4306401835","display_name":"Adelaide Research & Scholarship (AR&S) (University of Adelaide)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I5681781","host_organization_name":"The University of Adelaide","host_organization_lineage":["https://openalex.org/I5681781"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://dx.doi.org/10.1109/hldvt.2005.1568818","raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1994158727","https://openalex.org/W2048377933","https://openalex.org/W2097027490","https://openalex.org/W2098283416","https://openalex.org/W2102454528","https://openalex.org/W2103534830","https://openalex.org/W2111785162","https://openalex.org/W2133854172","https://openalex.org/W2162185868","https://openalex.org/W2187748717","https://openalex.org/W4232404949","https://openalex.org/W6648727905","https://openalex.org/W6679869287"],"related_works":["https://openalex.org/W2408673862","https://openalex.org/W3158858948","https://openalex.org/W128313926","https://openalex.org/W3091400564","https://openalex.org/W2368197002","https://openalex.org/W4247246286","https://openalex.org/W2560461391","https://openalex.org/W2154892829","https://openalex.org/W2121034600","https://openalex.org/W2365285506"],"abstract_inverted_index":{"Design":[0],"verification":[1,46,87],"is":[2,16,89],"crucial":[3],"for":[4],"successful":[5],"systems-on-chips":[6],"(SoCs).":[7],"However,":[8],"validating":[9],"and":[10],"proving":[11],"the":[12,21,31,34,81,103],"correctness":[13],"of":[14,53,56],"SoCs":[15],"often":[17],"a":[18,27,64],"bottleneck":[19],"in":[20,92],"design":[22],"project.":[23],"This":[24],"paper":[25],"presents":[26],"technique":[28],"to":[29,67,80,101],"test":[30,50,65,71,97,104],"SoC":[32,108],"at":[33],"system":[35,62],"level":[36,45],"using":[37],"software":[38,43,57,70],"application":[39,44],"based":[40],"programs.":[41],"Our":[42],"methodology":[47],"(SALVEM)":[48],"employs":[49],"programs":[51,72],"composed":[52],"dynamic":[54],"sequences":[55],"code":[58],"segments.":[59],"The":[60],"SALVEM":[61,78,94,96],"implements":[63],"generator":[66,105],"create":[68],"these":[69],"automatically.":[73],"Experiments":[74],"were":[75],"conducted":[76],"applying":[77],"tests":[79],"Altera":[82],"Nios":[83],"SoC.":[84],"A":[85],"feedback":[86],"flow":[88],"also":[90],"feasible":[91],"our":[93],"system.":[95],"runs":[98],"are":[99],"analyzed":[100],"direct":[102],"toward":[106],"important":[107],"scenarios.":[109]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}