{"id":"https://openalex.org/W2093461697","doi":"https://doi.org/10.1109/hldvt.2004.1431251","title":"On code coverage measurement for Verilog-A","display_name":"On code coverage measurement for Verilog-A","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2093461697","doi":"https://doi.org/10.1109/hldvt.2004.1431251","mag":"2093461697"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2004.1431251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2004.1431251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033017680","display_name":"Yuan-Bin Sha","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yuan-Bin Sha","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan","[Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan]","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076484580","display_name":"Mu-Shun Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mu-Shun Lee","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan","[Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan]","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052798292","display_name":"Chien\u2010Nan Jimmy Liu","orcid":"https://orcid.org/0000-0002-4907-898X"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Nan Jimmy Liu","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan","[Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan]","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5033017680"],"corresponding_institution_ids":["https://openalex.org/I22265921"],"apc_list":null,"apc_paid":null,"fwci":0.2633,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.5625734,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"115","last_page":"120"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8204998970031738},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7209736108779907},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6537346243858337},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.5758435726165771},{"id":"https://openalex.org/keywords/electronic-circuit-design","display_name":"Electronic circuit design","score":0.5475547909736633},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.537630558013916},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5308117866516113},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5072583556175232},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4992496967315674},{"id":"https://openalex.org/keywords/completeness","display_name":"Completeness (order theory)","score":0.48929211497306824},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.44262567162513733},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.38354480266571045},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.33662062883377075},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.264137327671051},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19051936268806458},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17947983741760254},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11108475923538208},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.09508439898490906},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07548615336418152},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07194283604621887}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8204998970031738},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7209736108779907},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6537346243858337},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.5758435726165771},{"id":"https://openalex.org/C99149447","wikidata":"https://www.wikidata.org/wiki/Q5358339","display_name":"Electronic circuit design","level":3,"score":0.5475547909736633},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.537630558013916},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5308117866516113},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5072583556175232},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4992496967315674},{"id":"https://openalex.org/C17231256","wikidata":"https://www.wikidata.org/wiki/Q5156540","display_name":"Completeness (order theory)","level":2,"score":0.48929211497306824},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.44262567162513733},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.38354480266571045},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.33662062883377075},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.264137327671051},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19051936268806458},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17947983741760254},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11108475923538208},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09508439898490906},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07548615336418152},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07194283604621887},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2004.1431251","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2004.1431251","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2000557929","https://openalex.org/W2022371756","https://openalex.org/W2026584294","https://openalex.org/W2054187805","https://openalex.org/W4250319054"],"related_works":["https://openalex.org/W1903717746","https://openalex.org/W2107517480","https://openalex.org/W2082283494","https://openalex.org/W2383788109","https://openalex.org/W2389932690","https://openalex.org/W1517999358","https://openalex.org/W2165480138","https://openalex.org/W2382083227","https://openalex.org/W2144390025","https://openalex.org/W2535987264"],"abstract_inverted_index":{"In":[0],"order":[1],"to":[2,20,48,65,88,118],"verify":[3,49],"the":[4,32,50,77,102,105,129,132],"integration":[5],"of":[6,52,82,104,131],"digital":[7,33,40],"circuits":[8,11,23,34],"and":[9,79],"analog":[10,22,57],"in":[12,36,70,108],"a":[13,94],"SOC":[14],"design,":[15],"HDL-A":[16],"languages":[17],"are":[18,60],"proposed":[19],"describe":[21],"such":[24],"that":[25],"they":[26],"can":[27,124],"be":[28],"simulated":[29],"together":[30],"with":[31],"described":[35],"HDL":[37,53],"code.":[38,90],"For":[39],"circuits,":[41],"coverage-driven":[42],"approach":[43],"has":[44],"been":[45],"widely":[46],"used":[47],"quality":[51],"designs.":[54,110],"However,":[55],"for":[56,100],"models,":[58],"there":[59],"still":[61],"no":[62],"suitable":[63],"solutions":[64],"gauge":[66],"their":[67],"quality.":[68],"Therefore,":[69],"this":[71,112],"paper,":[72],"we":[73,123],"will":[74],"first":[75],"discuss":[76],"feasibility":[78],"its":[80],"meaning":[81],"applying":[83],"some":[84],"existing":[85,119],"coverage":[86,96,113,121],"metrics":[87],"Verilog-A":[89,109,133],"We":[91],"also":[92],"propose":[93],"new":[95],"metric,":[97],"frequency":[98,106],"coverage,":[99],"checking":[101],"completeness":[103],"response":[107],"Using":[111],"metric":[114],"as":[115],"an":[116],"assistant":[117],"code":[120],"metrics,":[122],"have":[125],"more":[126],"confidence":[127],"on":[128],"correctness":[130],"descriptions":[134],"at":[135],"different":[136],"situations.":[137]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}