{"id":"https://openalex.org/W1494751629","doi":"https://doi.org/10.1109/hldvt.2002.1224438","title":"Alignability equivalence of synchronous sequential circuits","display_name":"Alignability equivalence of synchronous sequential circuits","publication_year":2003,"publication_date":"2003-10-01","ids":{"openalex":"https://openalex.org/W1494751629","doi":"https://doi.org/10.1109/hldvt.2002.1224438","mag":"1494751629"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2002.1224438","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2002.1224438","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014949895","display_name":"Amnon Rosenmann","orcid":"https://orcid.org/0000-0003-0255-0885"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Rosenmann","raw_affiliation_strings":["Design Technology Division, Logic and Validation Technology, Haifa, Israel","Dept. of Logic & Validation Technol., Intel, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Design Technology Division, Logic and Validation Technology, Haifa, Israel","institution_ids":[]},{"raw_affiliation_string":"Dept. of Logic & Validation Technol., Intel, Haifa, Israel","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068008369","display_name":"Ziyad Hanna","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Z. Hanna","raw_affiliation_strings":["Design Technology Division, Logic and Validation Technology, Haifa, Israel","Dept. of Logic & Validation Technol., Intel, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Design Technology Division, Logic and Validation Technology, Haifa, Israel","institution_ids":[]},{"raw_affiliation_string":"Dept. of Logic & Validation Technol., Intel, Haifa, Israel","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5014949895"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.127,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.86252523,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"111","last_page":"114"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11450","display_name":"Model-Driven Software Engineering Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8215866088867188},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.7912915945053101},{"id":"https://openalex.org/keywords/initialization","display_name":"Initialization","score":0.6809699535369873},{"id":"https://openalex.org/keywords/pentium","display_name":"Pentium","score":0.6278968453407288},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6256574392318726},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.6226052045822144},{"id":"https://openalex.org/keywords/symbolic-trajectory-evaluation","display_name":"Symbolic trajectory evaluation","score":0.6148439645767212},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.5168098211288452},{"id":"https://openalex.org/keywords/reachability","display_name":"Reachability","score":0.5124969482421875},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.5065699815750122},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4751301109790802},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3557819128036499},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3491952121257782},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.34227606654167175},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3174799978733063},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21780672669410706}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8215866088867188},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.7912915945053101},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.6809699535369873},{"id":"https://openalex.org/C46268123","wikidata":"https://www.wikidata.org/wiki/Q214314","display_name":"Pentium","level":2,"score":0.6278968453407288},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6256574392318726},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.6226052045822144},{"id":"https://openalex.org/C23123167","wikidata":"https://www.wikidata.org/wiki/Q7661193","display_name":"Symbolic trajectory evaluation","level":3,"score":0.6148439645767212},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.5168098211288452},{"id":"https://openalex.org/C136643341","wikidata":"https://www.wikidata.org/wiki/Q1361526","display_name":"Reachability","level":2,"score":0.5124969482421875},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.5065699815750122},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4751301109790802},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3557819128036499},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3491952121257782},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.34227606654167175},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3174799978733063},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21780672669410706},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2002.1224438","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2002.1224438","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1572774147","https://openalex.org/W1791573659","https://openalex.org/W2000040332","https://openalex.org/W2091732076","https://openalex.org/W2122885204","https://openalex.org/W2128893140","https://openalex.org/W2131033826","https://openalex.org/W2133582499","https://openalex.org/W2141579583","https://openalex.org/W2161017149","https://openalex.org/W2626969502"],"related_works":["https://openalex.org/W2114398233","https://openalex.org/W2122355433","https://openalex.org/W2134741216","https://openalex.org/W2109238268","https://openalex.org/W1520389894","https://openalex.org/W2926401818","https://openalex.org/W1556238795","https://openalex.org/W2081719483","https://openalex.org/W2161772051","https://openalex.org/W2130540187"],"abstract_inverted_index":{"Sequential":[0],"verification":[1,198],"is":[2,32,42],"a":[3,144],"well":[4],"known":[5],"research":[6,39],"framework":[7],"that":[8,41,150],"has":[9,175],"attracted":[10],"many":[11],"researchers":[12,56],"in":[13,57,195],"the":[14,21,35,88,91,119,131,166],"aca":[15],"demic":[16],"and":[17,37,63,67,70,73,76,81,98,109,147,156],"industrial":[18,51,137],"worlds":[19],"during":[20],"last":[22],"few":[23],"decades.":[24],"In":[25,139],"this":[26,58,85,140],"framework,":[27],"initialization":[28],"of":[29,34,90,134,172],"synchronous":[30],"models":[31,183],"one":[33],"fundamental":[36],"challenging":[38],"topics":[40],"difficult":[43],"to":[44,79,84,129,161],"solve,":[45],"especially":[46,126],"when":[47,127],"talking":[48,113],"about":[49,114],"large":[50,136],"strengths":[52],"hardware":[53,115],"models.":[54],"Many":[55],"domain":[59],"such":[60],"as":[61],"Pomeranz":[62],"Reddy":[64],"(1994),":[65,75],"Pixley":[66],"Beihl":[68],"(1991),":[69],"Pixley,":[71],"Jeong":[72],"Hachtel":[74],"others":[77],"tried":[78],"analyze":[80],"propose":[82,143],"solutions":[83],"problem,":[86],"however":[87],"majority":[89],"approaches":[92],"used":[93],"were":[94],"based":[95],"on":[96,178],"BDDs":[97],"classical":[99],"reachability":[100],"analysis":[101],"methods,":[102],"which":[103],"by":[104],"nature":[105],"suffer":[106],"from":[107,184],"capacity":[108],"complexity":[110],"limits.":[111],"When":[112],"formal":[116],"equivalence":[117,133,168],"verification,":[118],"Initialization":[120],"issue":[121],"becomes":[122],"even":[123],"more":[124],"complex":[125,179],"trying":[128],"verify":[130],"logic":[132],"two":[135],"circuits.":[138],"note":[141],"we":[142],"new":[145],"adaptive":[146],"iterative":[148],"approach":[149],"combines":[151],"various":[152],"symbolic":[153],"simulation":[154],"techniques":[155],"bounded":[157],"model":[158],"checking":[159],"algorithms":[160],"initialize":[162],"sequential":[163,182,197],"circuits":[164],"for":[165],"alignability":[167],"verification.":[169],"The":[170],"novelty":[171],"our":[173],"method":[174],"been":[176],"employed":[177],"real":[180],"life":[181],"Intel":[185],"lead":[186],"Pentium":[187],"processor":[188],"designs.":[189],"These":[190],"methods":[191],"are":[192],"already":[193],"implemented":[194],"Intel's":[196],"engine,":[199],"Insight.":[200]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}