{"id":"https://openalex.org/W1967626924","doi":"https://doi.org/10.1109/hipc.2011.6152738","title":"Implementing a hybrid SRAM / eDRAM NUCA architecture","display_name":"Implementing a hybrid SRAM / eDRAM NUCA architecture","publication_year":2011,"publication_date":"2011-12-01","ids":{"openalex":"https://openalex.org/W1967626924","doi":"https://doi.org/10.1109/hipc.2011.6152738","mag":"1967626924"},"language":"en","primary_location":{"id":"doi:10.1109/hipc.2011.6152738","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hipc.2011.6152738","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 18th International Conference on High Performance Computing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/2117/13932","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024347895","display_name":"Javier Lira","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Javier Lira","raw_affiliation_strings":["Department of Computer Architecture, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","Dept. of Computer Architecture, Universitat Polit\u00e8cnica de Catalunya, 08034 Barcelona, Spain#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Dept. of Computer Architecture, Universitat Polit\u00e8cnica de Catalunya, 08034 Barcelona, Spain#TAB#","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091529284","display_name":"Carlos Molina","orcid":"https://orcid.org/0000-0003-1955-0128"},"institutions":[{"id":"https://openalex.org/I55952717","display_name":"Universitat Rovira i Virgili","ror":"https://ror.org/00g5sqv46","country_code":"ES","type":"education","lineage":["https://openalex.org/I55952717"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Carlos Molina","raw_affiliation_strings":["Department of Computer Engineering, Universitat Rovira i Virgili, Tarragona, Spain","Dept. of Computer Engineering, Universitat Rovira i Virgili, 43007 Tarragona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Rovira i Virgili, Tarragona, Spain","institution_ids":["https://openalex.org/I55952717"]},{"raw_affiliation_string":"Dept. of Computer Engineering, Universitat Rovira i Virgili, 43007 Tarragona, Spain","institution_ids":["https://openalex.org/I55952717"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026496503","display_name":"David Brooks","orcid":"https://orcid.org/0000-0002-0662-7889"},"institutions":[{"id":"https://openalex.org/I136199984","display_name":"Harvard University","ror":"https://ror.org/03vek6s52","country_code":"US","type":"education","lineage":["https://openalex.org/I136199984"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Brooks","raw_affiliation_strings":["School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA","School of Engineering and Applied Sciences, Harvard University, 02138 Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA","institution_ids":["https://openalex.org/I136199984"]},{"raw_affiliation_string":"School of Engineering and Applied Sciences, Harvard University, 02138 Cambridge, MA, USA","institution_ids":["https://openalex.org/I136199984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100733331","display_name":"Antonio Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-0009-0996"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210136471","display_name":"FC Barcelona","ror":"https://ror.org/04bpz1v84","country_code":"ES","type":"other","lineage":["https://openalex.org/I4210136471"]},{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES","US"],"is_corresponding":false,"raw_author_name":"Antonio Gonzalez","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain","Intel Barcelona Research Center, Intel Labs - UPC, 08034 Barcelona, Spain#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Laboratories, UPC, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848","https://openalex.org/I4210136471"]},{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Labs - UPC, 08034 Barcelona, Spain#TAB#","institution_ids":["https://openalex.org/I9617848","https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.061,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.87067378,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"35?2","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.775968074798584},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7087993025779724},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7062082290649414},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7042757272720337},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6447786092758179},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5159702897071838},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4794656038284302},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4702683091163635},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45340225100517273},{"id":"https://openalex.org/keywords/ibm","display_name":"IBM","score":0.4516274034976959},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44910383224487305},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44015198945999146},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4284363389015198},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3824765682220459},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3552902340888977},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.25032317638397217},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22197628021240234},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.15419068932533264}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.775968074798584},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7087993025779724},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7062082290649414},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7042757272720337},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6447786092758179},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5159702897071838},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4794656038284302},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4702683091163635},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45340225100517273},{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.4516274034976959},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44910383224487305},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44015198945999146},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4284363389015198},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3824765682220459},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3552902340888977},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.25032317638397217},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22197628021240234},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.15419068932533264},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/hipc.2011.6152738","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hipc.2011.6152738","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 18th International Conference on High Performance Computing","raw_type":"proceedings-article"},{"id":"pmh:oai:dnet:upcommonspor::741e972417bd2fd086ec5f346d009d06","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/13932","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/draft"},{"id":"pmh:oai:upcommons.upc.edu:2117/13932","is_oa":true,"landing_page_url":"https://hdl.handle.net/2117/13932","pdf_url":null,"source":{"id":"https://openalex.org/S4377196262","display_name":"UPCommons institutional repository (Universitat Polit\u00e8cnica de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I9617848","host_organization_name":"Universitat Polit\u00e8cnica de Catalunya","host_organization_lineage":["https://openalex.org/I9617848"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/report"}],"best_oa_location":{"id":"pmh:oai:dnet:upcommonspor::741e972417bd2fd086ec5f346d009d06","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/13932","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/draft"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1964061332","https://openalex.org/W1978187377","https://openalex.org/W2047043979","https://openalex.org/W2048588974","https://openalex.org/W2064977311","https://openalex.org/W2074113453","https://openalex.org/W2084007230","https://openalex.org/W2084416612","https://openalex.org/W2096864363","https://openalex.org/W2102387714","https://openalex.org/W2110999128","https://openalex.org/W2114429886","https://openalex.org/W2120635877","https://openalex.org/W2126372249","https://openalex.org/W2131054871","https://openalex.org/W2131081741","https://openalex.org/W2147743629","https://openalex.org/W2153378664","https://openalex.org/W2164264749","https://openalex.org/W2169875292","https://openalex.org/W3147067924","https://openalex.org/W4235990555","https://openalex.org/W4236258190","https://openalex.org/W4248310916","https://openalex.org/W4253202538","https://openalex.org/W6641193217","https://openalex.org/W6675224354"],"related_works":["https://openalex.org/W2516517078","https://openalex.org/W1974599144","https://openalex.org/W2150909864","https://openalex.org/W3146763006","https://openalex.org/W4382618825","https://openalex.org/W2161286015","https://openalex.org/W4384572207","https://openalex.org/W4211178602","https://openalex.org/W4386903460","https://openalex.org/W2900372418"],"abstract_inverted_index":{"Advances":[0],"in":[1,22,91,129,133,216],"technology":[2,16],"allowed":[3],"for":[4],"integrating":[5],"DRAM-like":[6],"structures":[7],"into":[8],"the":[9,44,54,67,87,102,152,205,212],"chip,":[10],"called":[11],"embedded":[12],"DRAM":[13],"(eDRAM).":[14],"This":[15],"has":[17],"already":[18],"been":[19],"successfully":[20],"implemented":[21],"some":[23],"GPUs":[24],"and":[25,77,137,192],"other":[26],"graphic-intensive":[27],"SoC,":[28],"like":[29],"game":[30],"consoles.":[31],"The":[32],"most":[33],"recent":[34],"processor":[35,47],"from":[36,158],"IBM":[37],"<sup":[38],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[39],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u00ae</sup>":[40],",":[41],"POWER7,":[42],"is":[43],"first":[45],"general-purpose":[46],"that":[48,65,84,99,116,148,164],"integrates":[49],"an":[50,217],"eDRAM":[51,142,169],"module":[52],"on":[53,115],"chip.":[55],"In":[56],"this":[57],"paper,":[58],"we":[59,118,198,208],"propose":[60,119],"a":[61,94,120,159,165,179],"hybrid":[62,213],"cache":[63,105,154,171,181],"architecture":[64],"exploits":[66],"main":[68],"features":[69],"of":[70,75,80,97,135,183,221],"both":[71],"memory":[72],"technologies,":[73],"speed":[74],"SRAM":[76,139,160,167,185],"high":[78,88,95],"density":[79],"eDRAM.":[81],"We":[82,162],"demonstrate,":[83],"due":[85],"to":[86,101,151,203],"locality":[89],"found":[90],"emerging":[92],"applications,":[93],"percentage":[96],"data":[98,125,145],"enters":[100],"on-chip":[103],"last-level":[104],"are":[106,112,127],"not":[107],"accessed":[108],"again":[109],"before":[110],"they":[111],"evicted.":[113],"Based":[114],"observation,":[117],"placement":[121],"scheme":[122],"where":[123],"re-accessed":[124],"blocks":[126],"stored":[128],"fast,":[130],"but":[131,187],"costly":[132],"terms":[134],"area":[136,189,206],"power,":[138],"banks,":[140,186],"while":[141],"banks":[143],"store":[144],"blo":[146],"cks":[147],"just":[149],"arrive":[150],"NUCA":[153,170,180],"or":[155],"were":[156],"demoted":[157],"bank.":[161],"show":[163],"well-balanced":[166],"/":[168],"can":[172],"achieve":[173],"similar":[174],"performance":[175,219],"results":[176],"than":[177],"using":[178,211],"composed":[182],"only":[184],"reduces":[188],"by":[190,195,210],"15%":[191],"power":[193],"consumed":[194],"10%.":[196],"Furthermore,":[197],"also":[199],"explore":[200],"several":[201],"alternatives":[202],"exploit":[204],"reduction":[207],"gain":[209],"architecture,":[214],"resulting":[215],"overall":[218],"improvement":[220],"4%.":[222]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}