{"id":"https://openalex.org/W2096336201","doi":"https://doi.org/10.1109/hicss.2003.1174811","title":"An approach to the introduction of formal validation in an asynchronous circuit design flow","display_name":"An approach to the introduction of formal validation in an asynchronous circuit design flow","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2096336201","doi":"https://doi.org/10.1109/hicss.2003.1174811","mag":"2096336201"},"language":"en","primary_location":{"id":"doi:10.1109/hicss.2003.1174811","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.2003.1174811","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063371658","display_name":"D. Borrione","orcid":"https://orcid.org/0000-0002-4856-453X"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"D. Borrione","raw_affiliation_strings":["VDS group, TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"VDS group, TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064920153","display_name":"Menouer Boubekeur","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"M. Boubekeur","raw_affiliation_strings":["VDS group, TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"VDS group, TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071935946","display_name":"Emil Dumitrescu","orcid":"https://orcid.org/0000-0001-6614-4873"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"E. Dumitrescu","raw_affiliation_strings":["VDS group, TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"VDS group, TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017617798","display_name":"Marc Renaudin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"M. Renaudin","raw_affiliation_strings":["TIMA Laboratory, CIS group, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, CIS group, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059332865","display_name":"Jean-Baptiste Rigaud","orcid":"https://orcid.org/0000-0001-7394-5345"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J.-B. Rigaud","raw_affiliation_strings":["TIMA Laboratory, CIS group, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, CIS group, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105857255","display_name":"S. Sirianni","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"S. Sirianni","raw_affiliation_strings":["TIMA Laboratory, CIS group, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, CIS group, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5063371658"],"corresponding_institution_ids":["https://openalex.org/I4210087012"],"apc_list":null,"apc_paid":null,"fwci":1.4547,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.82522148,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"32","issue":null,"first_page":"10 pp.","last_page":"10 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8625834584236145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7998000383377075},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6988794207572937},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6791625022888184},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6236459612846375},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.5942825078964233},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5831606984138489},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.5415272116661072},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.4253959059715271},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.4227215349674225},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40306907892227173},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.38697540760040283},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18211796879768372},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1597539186477661},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1255064308643341},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08798480033874512}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8625834584236145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7998000383377075},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6988794207572937},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6791625022888184},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6236459612846375},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.5942825078964233},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5831606984138489},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.5415272116661072},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.4253959059715271},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.4227215349674225},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40306907892227173},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.38697540760040283},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18211796879768372},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1597539186477661},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1255064308643341},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08798480033874512},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/hicss.2003.1174811","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.2003.1174811","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.72.8089","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.72.8089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.hicss.hawaii.edu/HICSS36/HICSSpapers/STFME04.pdf","raw_type":"text"},{"id":"pmh:oai:HAL:hal-00009578v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00009578","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"36th Hawaii International Conference on Systems Sciences. 6-9 Jan, 2003, Big Island, HI, United States. 10 pp., &#x27E8;10.1109/HICSS.2003.1174811&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W33571320","https://openalex.org/W1481876205","https://openalex.org/W1489517620","https://openalex.org/W1543243434","https://openalex.org/W1585465727","https://openalex.org/W1589311678","https://openalex.org/W1595213177","https://openalex.org/W1599120076","https://openalex.org/W1765538419","https://openalex.org/W1951899050","https://openalex.org/W2099103090","https://openalex.org/W2099620341","https://openalex.org/W2100382727","https://openalex.org/W2104105510","https://openalex.org/W2122875134","https://openalex.org/W2145414321","https://openalex.org/W2155327371","https://openalex.org/W2156947018","https://openalex.org/W2169131413","https://openalex.org/W2176300081","https://openalex.org/W2340735175","https://openalex.org/W2938366666","https://openalex.org/W3144368627","https://openalex.org/W4211008702","https://openalex.org/W4230354049","https://openalex.org/W4242530255","https://openalex.org/W6635287215","https://openalex.org/W6637799165","https://openalex.org/W6640693055","https://openalex.org/W6812766823"],"related_works":["https://openalex.org/W4312516786","https://openalex.org/W1502478103","https://openalex.org/W2548837243","https://openalex.org/W1984298705","https://openalex.org/W4256596352","https://openalex.org/W4244147444","https://openalex.org/W2154582989","https://openalex.org/W2093491063","https://openalex.org/W2161215820","https://openalex.org/W2919987885"],"abstract_inverted_index":{"This":[0],"paper":[1],"discusses":[2],"the":[3,16,25,29],"integration":[4],"of":[5,19,28],"model-checking":[6],"inside":[7],"a":[8,57],"design":[9],"flow":[10],"for":[11],"quasi-delay":[12],"insensitive":[13],"circuits.":[14],"Both":[15],"formal":[17,26,40],"validation":[18],"an":[20],"asynchronous":[21,30,61],"behavioral":[22],"specification":[23],"and":[24,50],"verification":[27],"synthesis":[31],"result":[32],"are":[33],"considered.":[34],"The":[35,52],"method":[36],"follows":[37],"several":[38],"steps:":[39],"model":[41,43],"extraction,":[42],"simplification,":[44],"environment":[45],"modeling,":[46],"writing":[47],"temporal":[48],"properties":[49],"proof.":[51],"approach":[53],"is":[54],"illustrated":[55],"on":[56],"small,":[58],"yet":[59],"characteristic,":[60],"selection":[62],"circuit.":[63]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
