{"id":"https://openalex.org/W2118028367","doi":"https://doi.org/10.1109/hicss.2003.1174810","title":"Field modifiable architecture with FPGAs and its design/verification/debugging methodologies","display_name":"Field modifiable architecture with FPGAs and its design/verification/debugging methodologies","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2118028367","doi":"https://doi.org/10.1109/hicss.2003.1174810","mag":"2118028367"},"language":"en","primary_location":{"id":"doi:10.1109/hicss.2003.1174810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.2003.1174810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Fujita","raw_affiliation_strings":["University of Tokyo, Japan","Tokyo, University, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Tokyo, University, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050673369","display_name":"Setsuko Komatsu","orcid":"https://orcid.org/0000-0002-4514-357X"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Komatsu","raw_affiliation_strings":["University of Tokyo, Japan","Tokyo, University, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Tokyo, University, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032101050","display_name":"Shotaro Saito","orcid":"https://orcid.org/0000-0003-1133-0091"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Saito","raw_affiliation_strings":["University of Tokyo, Japan","Tokyo, University, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Tokyo, University, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037874806","display_name":"K. Seto","orcid":"https://orcid.org/0000-0001-9043-7019"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Seto","raw_affiliation_strings":["University of Tokyo, Japan","Tokyo, University, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Tokyo, University, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044331863","display_name":"Thanyapat Sakunkonchak","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Sakunkonchak","raw_affiliation_strings":["University of Tokyo, Japan","Tokyo, University, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Tokyo, University, Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043187145","display_name":"Yoshitsugu Kojima","orcid":"https://orcid.org/0000-0003-3466-4908"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Kojima","raw_affiliation_strings":["University of Tokyo, Japan","Tokyo, University, Japan"],"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Tokyo, University, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5027837299"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.17539757,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"10 pp.","last_page":"10 pp."},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7300115823745728},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7124754786491394},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6833829879760742},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.635941207408905},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6262214779853821},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6204794645309448},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.6032872200012207},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5832972526550293},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5033127665519714},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.48265963792800903},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.45065566897392273},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4375948905944824},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4216330051422119},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.41622138023376465},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4053933322429657}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7300115823745728},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7124754786491394},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6833829879760742},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.635941207408905},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6262214779853821},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6204794645309448},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.6032872200012207},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5832972526550293},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5033127665519714},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.48265963792800903},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.45065566897392273},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4375948905944824},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4216330051422119},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.41622138023376465},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4053933322429657},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/hicss.2003.1174810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.2003.1174810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.114.5410","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.114.5410","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://csdl.computer.org/comp/proceedings/hicss/2003/1874/09/187490279a.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.3.2877","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.2877","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.hicss.hawaii.edu/HICSS36/HICSSpapers/STFME03.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W74242707","https://openalex.org/W1485597611","https://openalex.org/W1491178396","https://openalex.org/W1498455513","https://openalex.org/W1550131357","https://openalex.org/W1597226399","https://openalex.org/W1751719170","https://openalex.org/W2059056208","https://openalex.org/W2061438988","https://openalex.org/W2080267935","https://openalex.org/W2086393337","https://openalex.org/W2120525597","https://openalex.org/W2148777220","https://openalex.org/W2152016786","https://openalex.org/W2155001141","https://openalex.org/W3150845164","https://openalex.org/W4233649183","https://openalex.org/W6603049948"],"related_works":["https://openalex.org/W4244547561","https://openalex.org/W2149478331","https://openalex.org/W2536819812","https://openalex.org/W4232787574","https://openalex.org/W2082795709","https://openalex.org/W1886739854","https://openalex.org/W3000479596","https://openalex.org/W2102468800","https://openalex.org/W3151908233","https://openalex.org/W1550641714"],"abstract_inverted_index":{"In":[0,37],"the":[1,17,27,73,79,83,100,103,106,119],"age":[2],"of":[3,26,29,34,49,72,82,102,108,140],"highly":[4],"integrated":[5],"system":[6],"LSIs,":[7],"design":[8,109],"methodologies":[9],"for":[10,111],"shorter":[11],"time-to-market":[12],"and":[13,53,61,89,105,143],"higher":[14],"re-programmability":[15],"after":[16],"chip":[18,153],"fabrications":[19],"are":[20],"now":[21],"key":[22],"research":[23],"issues":[24],"because":[25],"difficulty":[28],"complete":[30],"verification":[31],"before":[32],"tape-out":[33],"LSI":[35],"designs.":[36],"this":[38],"paper,":[39],"we":[40],"first":[41],"introduce":[42],"an":[43,54],"IP-based":[44],"VLSI":[45],"architecture":[46,121,125,132],"that":[47,130,144],"consists":[48],"a":[50,64],"main":[51],"processor":[52],"additional":[55],"hardware":[56,85],"(both":[57],"custom":[58],"hard":[59,115],"macros":[60],"FPGA":[62],"on":[63],"single":[65],"chip)":[66],"specialized":[67,84],"to":[68],"be":[69,149],"in":[70,99,138],"charge":[71],"specific":[74],"instructions.":[75],"We":[76,117],"further":[77],"replace":[78],"controller":[80],"circuits":[81],"with":[86],"compact":[87],"micro-controllers":[88],"memories":[90],"by":[91,114],"using":[92],"IP":[93],"libraries":[94],"(hard":[95],"macros),":[96],"which":[97],"results":[98,128],"increase":[101],"debuggability":[104],"flexibility":[107],"even":[110],"computations":[112],"realized":[113],"macros.":[116],"call":[118],"proposed":[120],"as":[122],"field":[123],"modifiable":[124],"(FMA).":[126],"Experimental":[127],"confirm":[129],"our":[131],"can":[133,148],"achieve":[134],"significant":[135],"performance":[136],"improvement":[137],"terms":[139],"execution":[141],"cycles":[142],"EC":[145],"(engineering":[146],"change)":[147],"successfully":[150],"accommodated":[151],"\"after\"":[152],"fabrications.":[154]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
