{"id":"https://openalex.org/W2025852841","doi":"https://doi.org/10.1109/globalsip.2013.6736977","title":"A framework to improve programmability of low power many-core processor for scalable DSP application","display_name":"A framework to improve programmability of low power many-core processor for scalable DSP application","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2025852841","doi":"https://doi.org/10.1109/globalsip.2013.6736977","mag":"2025852841"},"language":"en","primary_location":{"id":"doi:10.1109/globalsip.2013.6736977","is_oa":false,"landing_page_url":"https://doi.org/10.1109/globalsip.2013.6736977","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE Global Conference on Signal and Information Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101677729","display_name":"Tong Lin","orcid":"https://orcid.org/0000-0002-8112-0439"},"institutions":[{"id":"https://openalex.org/I4210127573","display_name":"Coherent Logix (United States)","ror":"https://ror.org/030kvkp19","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127573"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lin Tong","raw_affiliation_strings":["Coherent Logix, Incorporated, Austin, Texas, USA","Coherent Logix, Inc., Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Coherent Logix, Incorporated, Austin, Texas, USA","institution_ids":["https://openalex.org/I4210127573"]},{"raw_affiliation_string":"Coherent Logix, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I4210127573"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110046216","display_name":"Martin Hunt","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127573","display_name":"Coherent Logix (United States)","ror":"https://ror.org/030kvkp19","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127573"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin Hunt","raw_affiliation_strings":["Coherent Logix, Incorporated, Austin, Texas, USA","Coherent Logix, Inc., Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Coherent Logix, Incorporated, Austin, Texas, USA","institution_ids":["https://openalex.org/I4210127573"]},{"raw_affiliation_string":"Coherent Logix, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I4210127573"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09627971,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"658","last_page":"662"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7959682941436768},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.7907686829566956},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7299098372459412},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6505275368690491},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6110778450965881},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5615400075912476},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.527540922164917},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.490866482257843},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.42715099453926086},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36806291341781616},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32997530698776245},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2700410485267639},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12444701790809631},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08236795663833618}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7959682941436768},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.7907686829566956},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7299098372459412},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6505275368690491},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6110778450965881},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5615400075912476},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.527540922164917},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.490866482257843},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.42715099453926086},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36806291341781616},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32997530698776245},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2700410485267639},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12444701790809631},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08236795663833618},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/globalsip.2013.6736977","is_oa":false,"landing_page_url":"https://doi.org/10.1109/globalsip.2013.6736977","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE Global Conference on Signal and Information Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337367","display_name":"Division of Materials Research","ror":"https://ror.org/01pc7k308"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2011792082","https://openalex.org/W2043098580","https://openalex.org/W2053134101","https://openalex.org/W2074185362","https://openalex.org/W2127044011","https://openalex.org/W2323329537","https://openalex.org/W3141303489"],"related_works":["https://openalex.org/W1980880153","https://openalex.org/W2355267286","https://openalex.org/W4320067870","https://openalex.org/W4377693460","https://openalex.org/W2366499652","https://openalex.org/W2670084885","https://openalex.org/W2052664195","https://openalex.org/W2278140505","https://openalex.org/W1596119602","https://openalex.org/W3089727897"],"abstract_inverted_index":{"Embedded":[0],"and":[1,28,66,89,139,143,169,189],"ubiquitous":[2],"sensors":[3],"are":[4,19],"driving":[5],"industry":[6,63],"to":[7,25,35,39,73,95,135,153,163,182,186],"look":[8],"for":[9,13,22,191],"low":[10],"power":[11,171,195],"solutions":[12],"complex":[14],"DSP":[15,157,184],"algorithms;":[16],"system":[17],"engineers":[18],"also":[20],"looking":[21],"upgradable":[23],"capability":[24],"higher":[26,167],"throughput":[27,138],"algorithm":[29,158],"enhancements.":[30],"Many-core,":[31],"parallel":[32,101],"architectures":[33],"seem":[34],"be":[36],"a":[37,50,56,80,123,146,151,156,160,165],"solution":[38],"meet":[40],"these":[41],"interests":[42],"at":[43,84],"the":[44,53,85,97,112,117,120],"same":[45],"time.":[46],"However":[47],"it":[48],"introduces":[49],"challenging":[51],"problem:":[52],"programmability":[54],"of":[55,132,145],"many-core":[57,161],"processor":[58,207],"is":[59,71],"generally":[60],"perceived":[61],"by":[62,176],"as":[64],"difficult":[65],"inefficient.":[67],"A":[68],"new":[69],"framework":[70,78,149,174],"proposed":[72],"solve":[74,96],"this":[75,177],"challenge.":[76],"This":[77,148],"includes":[79],"dataflow":[81],"programming":[82,105],"methodology":[83],"top":[86],"level":[87,99],"design,":[88],"an":[90],"embedded":[91],"automatic":[92],"cell":[93,124],"generator":[94,125],"module":[98,121],"data":[100,113,129],"problem.":[102],"Data":[103],"flow":[104,114],"methodologies":[106],"avoid":[107],"explicit":[108],"synchronization":[109],"among":[110],"modules;":[111],"naturally":[115],"drives":[116],"synchronization.":[118],"At":[119],"level,":[122],"handles":[126],"application-specifics,":[127],"including":[128],"dependencies,":[130],"amount":[131],"parallelization":[133],"required":[134],"achieve":[136,164],"desired":[137],"complete":[140],"memory":[141],"management,":[142],"generation":[144],"library.":[147],"provides":[150],"path":[152],"quickly":[154],"develop":[155],"on":[159,197,209],"processor,":[162],"scalable,":[166],"throughput,":[168],"lower":[170],"solution.":[172],"The":[173],"demonstrated":[175],"paper":[178],"has":[179],"been":[180],"applied":[181],"various":[183],"algorithms":[185],"efficiently":[187],"parallelize":[188],"scale":[190],"different":[192],"through-put":[193],"or":[194],"requirement,":[196],"Coherent":[198],"Logix's":[199],"low-power":[200],"100":[201],"core":[202],"hx3100":[203],"<sup":[204,211],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[205,212],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">TM</sup>":[206,213],"based":[208],"HyperX":[210],"technology.":[214]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}