{"id":"https://openalex.org/W2786447084","doi":"https://doi.org/10.1109/fpt.2017.8280138","title":"A scalable hybrid architecture for high performance data-parallel applications","display_name":"A scalable hybrid architecture for high performance data-parallel applications","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2786447084","doi":"https://doi.org/10.1109/fpt.2017.8280138","mag":"2786447084"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2017.8280138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2017.8280138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Field Programmable Technology (ICFPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057193455","display_name":"Moucheng Yang","orcid":"https://orcid.org/0009-0009-2196-8073"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Moucheng Yang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048136162","display_name":"Jifang Jin","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jifang Jin","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072030922","display_name":"Zhehao Li","orcid":"https://orcid.org/0000-0003-0566-2567"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhehao Li","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103281733","display_name":"Xuegong Zhou","orcid":"https://orcid.org/0000-0003-4178-4094"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuegong Zhou","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100702016","display_name":"Shaojun Wang","orcid":"https://orcid.org/0000-0003-0467-8911"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaojun Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5057193455"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.2253,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54685082,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"191","last_page":"194"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7876204252243042},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6840954422950745},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6748252511024475},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6363617181777954},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5164337754249573},{"id":"https://openalex.org/keywords/parallel-architecture","display_name":"Parallel architecture","score":0.46311962604522705},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3429105579853058},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13969069719314575}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7876204252243042},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6840954422950745},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6748252511024475},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6363617181777954},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5164337754249573},{"id":"https://openalex.org/C2985918086","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel architecture","level":3,"score":0.46311962604522705},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3429105579853058},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13969069719314575},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2017.8280138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2017.8280138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Field Programmable Technology (ICFPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1563299586","https://openalex.org/W1675140429","https://openalex.org/W1972648069","https://openalex.org/W2008241424","https://openalex.org/W2015370416","https://openalex.org/W2122522028","https://openalex.org/W2154991996","https://openalex.org/W2173213060","https://openalex.org/W2260448916","https://openalex.org/W2525740295","https://openalex.org/W3120740533","https://openalex.org/W6727759651"],"related_works":["https://openalex.org/W2389214306","https://openalex.org/W4235240664","https://openalex.org/W2965083567","https://openalex.org/W1838576100","https://openalex.org/W2095886385","https://openalex.org/W4401278057","https://openalex.org/W2038503502","https://openalex.org/W2158228144","https://openalex.org/W206792560","https://openalex.org/W1965117583"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,75,151],"scalable":[4],"hybrid":[5],"architecture":[6,29,70],"for":[7,38,167],"high":[8],"performance":[9,44,141],"data-parallel":[10,80],"applications":[11,168],"on":[12,54,134,156,164],"tightly":[13],"coupled":[14],"shared-memory":[15],"CPU-FPGA":[16],"systems":[17],"such":[18],"as":[19,74,150],"the":[20,27,33,43,59,111,117,125,131,135],"Xilinx":[21],"Zynq":[22,165],"SoC.":[23],"The":[24,68],"aims":[25],"of":[26,35,100,114,116,124,127,169],"proposed":[28,69],"are:":[30],"1)to":[31],"simplify":[32],"development":[34],"hardware":[36,51,91,102,118,152],"acceleration":[37],"dataparallel":[39],"applications;":[40],"2)to":[41],"reach":[42],"limit":[45],"caused":[46,61],"by":[47,62],"memory":[48,128],"access":[49,129],"and/or":[50],"resource":[52],"available":[53,133],"an":[55,85],"FPGA;":[56],"3)to":[57],"reduce":[58],"overhead":[60],"task":[63,83,143],"scheduling":[64,144],"and":[65,130,145,178],"device":[66,146],"drivers.":[67],"can":[71],"be":[72],"used":[73],"generic":[76],"template":[77],"to":[78,89,106,139],"implement":[79],"applications.":[81],"Each":[82],"in":[84],"application":[86],"is":[87,94],"mapped":[88],"one":[90],"accelerator,":[92],"which":[93],"called":[95,154],"\u201ckernel\u201d.":[96],"Several":[97],"identical":[98],"instances":[99,115],"each":[101],"kernel":[103],"execute":[104],"concurrently":[105],"provide":[107],"parallelism.":[108],"By":[109],"deploying":[110],"maximum":[112],"number":[113],"kernel,":[119],"we":[120],"make":[121],"full":[122],"use":[123],"bandwidth":[126],"resources":[132],"FPGA.":[136],"In":[137],"order":[138],"improve":[140],"further,":[142],"drivers":[147],"are":[148],"implemented":[149],"scheduler":[153],"DmaScheduler":[155],"FPGA":[157,166,184],"hardware.":[158],"Experimental":[159],"results":[160],"show":[161],"2.93x-51.25x":[162],"speedup":[163],"image":[170],"processing,":[171],"Black":[172],"Scholes":[173],"option":[174],"pricing,":[175],"matrix":[176],"multiplication":[177],"clustering":[179],"algorithm,":[180],"compared":[181],"with":[182],"existing":[183],"implementations.":[185]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}