{"id":"https://openalex.org/W2777743316","doi":"https://doi.org/10.1109/fpt.2017.8280127","title":"Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs","display_name":"Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2777743316","doi":"https://doi.org/10.1109/fpt.2017.8280127","mag":"2777743316"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2017.8280127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2017.8280127","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Field Programmable Technology (ICFPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000955555","display_name":"Felix Winterstein","orcid":"https://orcid.org/0000-0002-2525-0693"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Felix Winterstein","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George Constantinides","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5000955555"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.4506,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.64079057,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"104","last_page":"111"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8687174320220947},{"id":"https://openalex.org/keywords/pointer","display_name":"Pointer (user interface)","score":0.6541038751602173},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5484946966171265},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4709053039550781},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46591758728027344},{"id":"https://openalex.org/keywords/address-space","display_name":"Address space","score":0.4640563726425171},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.42380380630493164},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.37774038314819336},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34298253059387207},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24398285150527954}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8687174320220947},{"id":"https://openalex.org/C150202949","wikidata":"https://www.wikidata.org/wiki/Q107602","display_name":"Pointer (user interface)","level":2,"score":0.6541038751602173},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5484946966171265},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4709053039550781},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46591758728027344},{"id":"https://openalex.org/C144240696","wikidata":"https://www.wikidata.org/wiki/Q367204","display_name":"Address space","level":2,"score":0.4640563726425171},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.42380380630493164},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.37774038314819336},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34298253059387207},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24398285150527954}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2017.8280127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2017.8280127","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Field Programmable Technology (ICFPT)","raw_type":"proceedings-article"},{"id":"pmh:oai:spiral.imperial.ac.uk:10044/1/53101","is_oa":false,"landing_page_url":"http://hdl.handle.net/10044/1/53101","pdf_url":null,"source":{"id":"https://openalex.org/S4306401396","display_name":"Spiral (Imperial College London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I47508984","host_organization_name":"Imperial College London","host_organization_lineage":["https://openalex.org/I47508984"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2017 International Conference on Field-Programmable Technology","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6499999761581421}],"awards":[{"id":"https://openalex.org/G7639885267","display_name":null,"funder_award_id":"EP/K034448/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G774180880","display_name":null,"funder_award_id":"EP/P010040/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320320005","display_name":"Royal Academy of Engineering","ror":"https://ror.org/0526snb40"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1972648069","https://openalex.org/W1997113918","https://openalex.org/W2099375606","https://openalex.org/W2100037312","https://openalex.org/W2104617021","https://openalex.org/W2125744812","https://openalex.org/W2162148292","https://openalex.org/W2280654368","https://openalex.org/W2613639279"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2030470867","https://openalex.org/W4285144448","https://openalex.org/W514290","https://openalex.org/W4253720183","https://openalex.org/W879469844","https://openalex.org/W1559683866","https://openalex.org/W2057854888"],"abstract_inverted_index":{"Heterogeneous":[0],"CPU-FPGA":[1,49],"systems":[2,9],"are":[3,34,41],"gaining":[4],"momentum":[5],"in":[6,12,36],"the":[7,13,18,23,48,60,83,103,110,145,160,169,177],"embedded":[8],"sector":[10],"and":[11,28,62,86,112,167,189,211],"data":[14,24,57,122,187,191],"center":[15],"market.":[16],"While":[17],"programming":[19,39,72,135],"abstractions":[20],"for":[21,43,51,148,155,163],"implementing":[22],"transfer":[25],"between":[26,59,82],"CPU":[27,61,85],"FPGA":[29,63,91],"(and":[30,125],"vice":[31],"versa)":[32],"that":[33,53,79,142],"available":[35],"today's":[37],"commercial":[38,152],"tools":[40],"well-suited":[42],"certain":[44],"types":[45],"of":[46,95,115,179],"applications,":[47],"communication":[50],"applications":[52],"share":[54,120],"complex":[55,121],"pointer-based":[56],"structures":[58,123,188],"remains":[64],"difficult":[65],"to":[66,119,176,182,194],"implement.":[67],"This":[68,157],"paper":[69,158],"focuses":[70],"on":[71],"environments":[73],"providing":[74],"a":[75,116,130,140,151],"virtual":[76,97],"memory":[77,98],"space":[78,162],"is":[80,100,209],"shared":[81,96],"host":[84],"one":[87],"(or":[88],"potentially":[89],"several)":[90],"devices.":[92],"One":[93],"example":[94],"(SVM)":[99],"defined":[101],"by":[102,127],"recent":[104],"OpenCL":[105,153,199],"2.0":[106],"standard.":[107],"SVM":[108,149,202],"allows":[109],"software":[111],"hardware":[113],"portion":[114],"hybrid":[117],"application":[118],"seamlessly":[124],"concurrently)":[126],"simply":[128],"passing":[129],"pointer,":[131],"which":[132],"greatly":[133],"eases":[134],"heterogeneous":[136],"systems.":[137],"We":[138,172],"present":[139],"framework":[141,208],"automatically":[143],"adds":[144],"physical":[146],"infrastructure":[147],"into":[150],"tool":[154],"FPGAs.":[156],"explores":[159],"design":[161,200],"these":[164],"building":[165],"blocks":[166],"studies":[168],"performance":[170],"impact.":[171],"show":[173],"that,":[174],"due":[175],"ability":[178],"SVM-enabled":[180],"implementations":[181],"avoid":[183],"artificially":[184],"sizing":[185],"dynamic":[186],"fetching":[190],"on-the-fly,":[192],"up":[193],"2x":[195],"speed-up":[196],"over":[197],"an":[198],"without":[201],"support":[203],"can":[204],"be":[205],"achieved.":[206],"Our":[207],"open-source":[210],"publicly":[212],"available.":[213]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}