{"id":"https://openalex.org/W2785583448","doi":"https://doi.org/10.1109/fpt.2017.8280114","title":"RBSA: Range-based simulated annealing for FPGA placement","display_name":"RBSA: Range-based simulated annealing for FPGA placement","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2785583448","doi":"https://doi.org/10.1109/fpt.2017.8280114","mag":"2785583448"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2017.8280114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2017.8280114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Field Programmable Technology (ICFPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042019568","display_name":"Junqi Yuan","orcid":"https://orcid.org/0000-0002-7996-6574"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Junqi Yuan","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103281733","display_name":"Xuegong Zhou","orcid":"https://orcid.org/0000-0003-4178-4094"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuegong Zhou","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070614875","display_name":"Yinshui Xia","orcid":"https://orcid.org/0000-0002-3831-3876"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yinshui Xia","raw_affiliation_strings":["Ningbo University, Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023402050","display_name":"Jianping Hu","orcid":"https://orcid.org/0000-0002-6469-1061"},"institutions":[{"id":"https://openalex.org/I109935558","display_name":"Ningbo University","ror":"https://ror.org/03et85d35","country_code":"CN","type":"education","lineage":["https://openalex.org/I109935558"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianping Hu","raw_affiliation_strings":["Ningbo University, Ningbo, China"],"affiliations":[{"raw_affiliation_string":"Ningbo University, Ningbo, China","institution_ids":["https://openalex.org/I109935558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5042019568"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.43,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.67178956,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"16","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7531660795211792},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7413098216056824},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.6588667035102844},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6402359008789062},{"id":"https://openalex.org/keywords/swap","display_name":"Swap (finance)","score":0.6125546097755432},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.520786702632904},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.4742932617664337},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4224611222743988},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4112628102302551},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3442647457122803},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3433346450328827},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28121417760849},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10516443848609924}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7531660795211792},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7413098216056824},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.6588667035102844},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6402359008789062},{"id":"https://openalex.org/C99821215","wikidata":"https://www.wikidata.org/wiki/Q1136583","display_name":"Swap (finance)","level":2,"score":0.6125546097755432},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.520786702632904},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.4742932617664337},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4224611222743988},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4112628102302551},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3442647457122803},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3433346450328827},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28121417760849},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10516443848609924},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2017.8280114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2017.8280114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Field Programmable Technology (ICFPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W62704612","https://openalex.org/W178407265","https://openalex.org/W1499164988","https://openalex.org/W1523051745","https://openalex.org/W1969308522","https://openalex.org/W1982368736","https://openalex.org/W1996746141","https://openalex.org/W2005602803","https://openalex.org/W2007015871","https://openalex.org/W2024060531","https://openalex.org/W2036436027","https://openalex.org/W2037524044","https://openalex.org/W2055078783","https://openalex.org/W2057839796","https://openalex.org/W2064997970","https://openalex.org/W2102502584","https://openalex.org/W2114820519","https://openalex.org/W2117082818","https://openalex.org/W2139637699","https://openalex.org/W2142356348","https://openalex.org/W2142613770","https://openalex.org/W2148535958","https://openalex.org/W2148948822","https://openalex.org/W2158961316","https://openalex.org/W2164340799","https://openalex.org/W2194944742","https://openalex.org/W3000171651","https://openalex.org/W3148293037","https://openalex.org/W4243050516","https://openalex.org/W6602503274","https://openalex.org/W6664331118","https://openalex.org/W6680692090","https://openalex.org/W6805452219"],"related_works":["https://openalex.org/W4313341326","https://openalex.org/W4282568311","https://openalex.org/W4313484792","https://openalex.org/W2951473296","https://openalex.org/W2883928845","https://openalex.org/W4288420200","https://openalex.org/W3145095675","https://openalex.org/W4285346947","https://openalex.org/W4365793791","https://openalex.org/W3134072570"],"abstract_inverted_index":{"Placement":[0],"has":[1,16],"always":[2],"been":[3,17],"the":[4,9,36,59,66,71,123,129,134],"most":[5],"time-consuming":[6],"part":[7],"in":[8],"FPGA":[10,29],"compilation":[11],"flow.":[12],"Traditional":[13],"simulated":[14],"annealing":[15],"unable":[18],"to":[19,57,88,103],"keep":[20],"pace":[21],"with":[22,122],"ever":[23],"increasing":[24],"sizes":[25],"of":[26,35,44,61,73,132],"designs":[27],"and":[28,64,84,111,137],"chip":[30],"resources.":[31],"Without":[32],"utilizing":[33],"information":[34],"circuit":[37],"topology,":[38],"it":[39],"relies":[40],"on":[41,100,119],"large":[42],"amounts":[43],"random":[45],"swap":[46,62,67],"operations,":[47],"which":[48,106],"are":[49],"time-costly.":[50],"This":[51,113],"paper":[52],"proposes":[53],"a":[54],"range-based":[55],"algorithm":[56],"improve":[58],"behavior":[60],"operations":[63],"limit":[65],"distances":[68],"by":[69],"introducing":[70],"concept":[72],"range":[74],"limiting":[75],"for":[76],"nets.":[77],"It":[78,140],"avoids":[79],"unnecessary":[80],"design":[81],"space":[82],"exploration,":[83],"thus":[85],"can":[86],"converge":[87],"near-optimal":[89],"solutions":[90],"much":[91],"more":[92],"quickly.":[93],"The":[94],"Titan":[95],"benchmarks":[96],"we":[97],"have":[98],"tested":[99],"contains":[101],"4K":[102],"30K":[104],"blocks,":[105],"include":[107],"LABs,":[108],"IOs,":[109],"DSPs":[110],"RAMs.":[112],"approach":[114],"achieves":[115],"2.05X":[116],"speed":[117],"up":[118],"average":[120],"compared":[121],"SA":[124],"from":[125],"VTR":[126],"while":[127],"preserving":[128],"placement":[130],"quality":[131],"both":[133],"wire":[135],"length":[136],"critical":[138],"path.":[139],"also":[141],"manifests":[142],"better":[143],"scalability":[144],"towards":[145],"larger":[146],"benchmarks.":[147]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
