{"id":"https://openalex.org/W2286366494","doi":"https://doi.org/10.1109/fpt.2015.7393141","title":"Custom-sized caches in application-specific memory hierarchies","display_name":"Custom-sized caches in application-specific memory hierarchies","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2286366494","doi":"https://doi.org/10.1109/fpt.2015.7393141","mag":"2286366494"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2015.7393141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2015.7393141","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Field Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000955555","display_name":"Felix Winterstein","orcid":"https://orcid.org/0000-0002-2525-0693"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Felix Winterstein","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027505039","display_name":"Kermin Fleming","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Kermin Fleming","raw_affiliation_strings":["SSG, Intel Corporation"],"affiliations":[{"raw_affiliation_string":"SSG, Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101767631","display_name":"Hsin-Jung Yang","orcid":"https://orcid.org/0000-0002-0990-7763"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hsin-Jung Yang","raw_affiliation_strings":["CSAIL, Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"CSAIL, Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002846450","display_name":"John Wickerson","orcid":"https://orcid.org/0000-0001-6735-5533"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"John Wickerson","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George Constantinides","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5000955555"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":1.6149,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.84410201,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"144","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8772341012954712},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6147053241729736},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5671515464782715},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.49583038687705994},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48716995120048523},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.47537627816200256},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.419174462556839},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41917330026626587},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.39135462045669556}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8772341012954712},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6147053241729736},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5671515464782715},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.49583038687705994},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48716995120048523},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.47537627816200256},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.419174462556839},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41917330026626587},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.39135462045669556}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2015.7393141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2015.7393141","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Field Programmable Technology (FPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1487184349","https://openalex.org/W1966693694","https://openalex.org/W1990525787","https://openalex.org/W1999489580","https://openalex.org/W2005022399","https://openalex.org/W2013594929","https://openalex.org/W2017546871","https://openalex.org/W2022128349","https://openalex.org/W2024612992","https://openalex.org/W2056971515","https://openalex.org/W2080380374","https://openalex.org/W2094966716","https://openalex.org/W2097537332","https://openalex.org/W2127788760","https://openalex.org/W2141280299","https://openalex.org/W2165972424","https://openalex.org/W2397454561","https://openalex.org/W2601686331","https://openalex.org/W2604383488","https://openalex.org/W3003468330","https://openalex.org/W4240313904","https://openalex.org/W4242953705","https://openalex.org/W6712681754"],"related_works":["https://openalex.org/W2167303720","https://openalex.org/W2012518269","https://openalex.org/W4243772489","https://openalex.org/W57688818","https://openalex.org/W2109715593","https://openalex.org/W1963899689","https://openalex.org/W4226093591","https://openalex.org/W1863436361","https://openalex.org/W4392546877","https://openalex.org/W2363750085"],"abstract_inverted_index":{"Developing":[0],"FPGA":[1,60,177],"implementations":[2,39,174],"with":[3,171],"an":[4,51,87,162,176],"input":[5],"specification":[6],"in":[7,69,183],"a":[8,19,26,66,118,139,181,196],"high-level":[9,36,119],"programming":[10],"language":[11],"such":[12],"as":[13],"C/C++":[14],"or":[15],"OpenCL":[16],"allows":[17],"for":[18,109],"substantially":[20],"shortened":[21],"design":[22,27],"cycle":[23],"compared":[24,194],"to":[25,50,63,71,137,146,161,188,195],"entry":[28],"at":[29],"register":[30],"transfer":[31],"level.":[32],"This":[33],"work":[34],"targets":[35],"synthesis":[37],"(HLS)":[38],"that":[40,152],"process":[41],"large":[42],"amounts":[43],"of":[44,58,75,82,112,129,142,156,186,205,216],"data":[45],"and":[46,86,101,179],"therefore":[47],"require":[48],"access":[49,127,150],"off-chip":[52],"memory.":[53,89],"We":[54,132,167,200],"leverage":[55],"the":[56,59,73,76,83,110,125,130,147,154,157,203,212,217],"customizability":[57],"on-chip":[61,113,163],"memory":[62,126,135,149,164],"automatically":[64,207],"construct":[65],"multi-cache":[67,158],"architecture":[68],"order":[70],"enhance":[72],"performance":[74,121,155],"interface":[77],"between":[78],"parallel":[79],"functional":[80],"units":[81],"HLS":[84],"core":[85],"external":[88],"Our":[90],"focus":[91],"is":[92],"on":[93,124,175,191,211],"automatic":[94],"cache":[95,120,143,198,209],"sizing.":[96,199],"Firstly,":[97],"our":[98,169,206],"technique":[99,170],"determines":[100],"uses":[102],"up":[103,187],"unused":[104],"left-over":[105],"block":[106],"RAM":[107],"resources":[108],"construction":[111],"caches.":[114],"Secondly,":[115],"we":[116],"devise":[117],"estimation":[122],"based":[123],"trace":[128,136],"program.":[131],"use":[133],"this":[134],"find":[138],"heterogeneous":[140],"configuration":[141],"sizes,":[144],"tailored":[145],"application's":[148],"characteristic,":[151],"maximizes":[153],"system":[159,210],"subject":[160],"resource":[165],"constraint.":[166],"evaluate":[168],"three":[172],"benchmark":[173],"board":[178],"obtain":[180],"reduction":[182],"execution":[184],"latency":[185],"2\u00d7":[189],"(1.5\u00d7":[190],"average)":[192],"when":[193],"one-size-fits-all":[197],"also":[201],"quantify":[202],"impact":[204],"generated":[208],"overall":[213],"energy":[214],"consumption":[215],"implementation.":[218]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}