{"id":"https://openalex.org/W2279391168","doi":"https://doi.org/10.1109/fpt.2015.7393130","title":"QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay","display_name":"QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2279391168","doi":"https://doi.org/10.1109/fpt.2015.7393130","mag":"2279391168"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2015.7393130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2015.7393130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Field Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100384309","display_name":"Cheng Liu","orcid":"https://orcid.org/0000-0002-5542-7306"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Cheng Liu","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, The University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, The University of Hong Kong","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056411319","display_name":"Ho-Cheung Ng","orcid":"https://orcid.org/0000-0002-5171-1318"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Ho-Cheung Ng","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, The University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, The University of Hong Kong","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020581824","display_name":"Hayden Kwok\u2010Hay So","orcid":null},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Hayden Kwok-Hay So","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, The University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, The University of Hong Kong","institution_ids":["https://openalex.org/I889458895"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100384309"],"corresponding_institution_ids":["https://openalex.org/I889458895"],"apc_list":null,"apc_paid":null,"fwci":5.8172,"has_fulltext":false,"cited_by_count":43,"citation_normalized_percentile":{"value":0.96613833,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"56","last_page":"63"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8231430053710938},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8182798624038696},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6677082180976868},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.6639726161956787},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5572086572647095},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5271287560462952},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5210408568382263},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.500615119934082},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.4960115849971771},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4438436031341553},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3943401277065277},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2480495274066925},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.1048499345779419}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8231430053710938},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8182798624038696},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6677082180976868},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.6639726161956787},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5572086572647095},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5271287560462952},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5210408568382263},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.500615119934082},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.4960115849971771},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4438436031341553},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3943401277065277},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2480495274066925},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.1048499345779419},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2015.7393130","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2015.7393130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Field Programmable Technology (FPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W81765945","https://openalex.org/W1485517334","https://openalex.org/W1885706698","https://openalex.org/W1970340536","https://openalex.org/W1972387588","https://openalex.org/W1976693023","https://openalex.org/W1990079240","https://openalex.org/W2008781896","https://openalex.org/W2008844983","https://openalex.org/W2018055497","https://openalex.org/W2023844339","https://openalex.org/W2041958163","https://openalex.org/W2047143252","https://openalex.org/W2051392577","https://openalex.org/W2052930524","https://openalex.org/W2062435236","https://openalex.org/W2064997970","https://openalex.org/W2069523538","https://openalex.org/W2081201959","https://openalex.org/W2096132155","https://openalex.org/W2099132653","https://openalex.org/W2105917387","https://openalex.org/W2107350738","https://openalex.org/W2115294662","https://openalex.org/W2121303892","https://openalex.org/W2133156997","https://openalex.org/W2138403270","https://openalex.org/W2139817798","https://openalex.org/W2150022482","https://openalex.org/W2151471392","https://openalex.org/W2160126455","https://openalex.org/W2244473793","https://openalex.org/W2554510265","https://openalex.org/W4256629673","https://openalex.org/W6603389453","https://openalex.org/W6690706171"],"related_works":["https://openalex.org/W4319430423","https://openalex.org/W4390224957","https://openalex.org/W2993910401","https://openalex.org/W4323831234","https://openalex.org/W2544043553","https://openalex.org/W2121309702","https://openalex.org/W1982685694","https://openalex.org/W49599899","https://openalex.org/W4311839959","https://openalex.org/W3217774925"],"abstract_inverted_index":{"The":[0],"use":[1,40,49],"of":[2,30,41,50,76,86,118,146,168,180],"FPGAs":[3],"as":[4,13],"compute":[5],"accelerators":[6,33,164],"has":[7],"been":[8],"demonstrated":[9],"by":[10],"numerous":[11],"researchers":[12],"an":[14],"effective":[15],"solution":[16],"to":[17,38,126,156,162,173],"meet":[18],"the":[19,27,39,48,51,60,74,83,127,138,147,157,166,178,181],"performance":[20,175],"requirement":[21],"across":[22],"many":[23],"application":[24],"domains.":[25],"However,":[26],"design":[28,53,91],"productivity":[29,92],"developing":[31],"FPGA":[32,63,99,139],"remains":[34],"much":[35],"lower":[36],"compared":[37],"a":[42,97,108,123,130,143,151,186],"typical":[43],"software":[44,183],"development":[45],"flow.":[46],"Although":[47],"high-level":[52,124],"tools":[54],"may":[55],"partly":[56],"alleviate":[57],"this":[58,90],"shortcoming,":[59],"lengthy":[61],"low-level":[62],"implementation":[64],"process":[65],"including":[66],"synthesis,":[67],"placing":[68],"and":[69,81,135,150],"routing":[70],"still":[71],"dramatically":[72],"limits":[73],"number":[75],"compile-debug-edit":[77],"cycles":[78],"per":[79],"day":[80],"hinders":[82],"widespread":[84],"adoption":[85],"FPGAs.":[87],"To":[88],"address":[89],"problem,":[93],"we":[94],"have":[95],"developed":[96],"rapid":[98,131,144],"loop":[100,125],"accelerator":[101,140],"generation":[102],"framework":[103],"called":[104],"QuickDough.":[105],"By":[106],"utilizing":[107],"soft":[109],"coarse-grained":[110],"reconfigurable":[111],"array":[112],"(SCGRA)":[113],"overlay":[114,128,153],"built":[115],"on":[116,185],"top":[117],"off-the-shelf":[119],"FPGAs,":[120],"it":[121],"compiles":[122],"through":[129,142],"operation":[132],"scheduling":[133,148],"first":[134],"then":[136],"generates":[137],"bitstream":[141],"integration":[145],"result":[149],"pre-built":[152],"bitstream.":[154],"According":[155],"experiments,":[158],"QuickDough":[159],"is":[160],"able":[161],"produce":[163],"in":[165],"order":[167],"seconds":[169],"while":[170],"achieving":[171],"up":[172],"9X":[174],"speedup":[176],"over":[177],"execution":[179],"same":[182],"running":[184],"hard":[187],"ARM":[188],"processor.":[189]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1}],"updated_date":"2026-02-26T06:29:33.603293","created_date":"2025-10-10T00:00:00"}