{"id":"https://openalex.org/W2286372582","doi":"https://doi.org/10.1109/fpt.2015.7393119","title":"FPGA Trax Solver based on a neural network design","display_name":"FPGA Trax Solver based on a neural network design","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2286372582","doi":"https://doi.org/10.1109/fpt.2015.7393119","mag":"2286372582"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2015.7393119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2015.7393119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Field Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108624634","display_name":"Takumi Fujimori","orcid":null},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Takumi Fujimori","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084314379","display_name":"Tomoya Akabe","orcid":"https://orcid.org/0000-0003-1816-5295"},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tomoya Akabe","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047739671","display_name":"Yoshizumi Ito","orcid":null},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshizumi Ito","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007528320","display_name":"Kouta Akagi","orcid":null},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kouta Akagi","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110451707","display_name":"Shinya Furukawa","orcid":null},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinya Furukawa","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088232510","display_name":"Hiroki Shinba","orcid":null},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroki Shinba","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039365632","display_name":"Aoi Tanibata","orcid":"https://orcid.org/0000-0001-8501-0563"},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Aoi Tanibata","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101887712","display_name":"Minoru Watanabe","orcid":"https://orcid.org/0000-0002-7452-3555"},"institutions":[{"id":"https://openalex.org/I1298590031","display_name":"Shizuoka University","ror":"https://ror.org/01w6wtk13","country_code":"JP","type":"education","lineage":["https://openalex.org/I1298590031"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Minoru Watanabe","raw_affiliation_strings":["Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering, Shizuoka University, Shizuoka, Japan","institution_ids":["https://openalex.org/I1298590031"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5108624634"],"corresponding_institution_ids":["https://openalex.org/I1298590031"],"apc_list":null,"apc_paid":null,"fwci":0.4314,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.77835267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"260","last_page":"263"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9908000230789185,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9249118566513062},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.74623703956604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7249244451522827},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5173118114471436},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48824384808540344},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.43245798349380493},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.42540639638900757},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41881972551345825},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36230552196502686},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3406860828399658},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19211342930793762},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.18221184611320496},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09962120652198792}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9249118566513062},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.74623703956604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7249244451522827},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5173118114471436},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48824384808540344},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.43245798349380493},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.42540639638900757},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41881972551345825},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36230552196502686},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3406860828399658},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19211342930793762},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.18221184611320496},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09962120652198792}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2015.7393119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2015.7393119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Field Programmable Technology (FPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W654563454","https://openalex.org/W2007981657","https://openalex.org/W2030388277","https://openalex.org/W2032767416","https://openalex.org/W2057410336","https://openalex.org/W2063848891","https://openalex.org/W2090840501","https://openalex.org/W2093335996","https://openalex.org/W2115503785","https://openalex.org/W2131933864","https://openalex.org/W2137089582","https://openalex.org/W2167671418","https://openalex.org/W6621901308"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2113648965","https://openalex.org/W2155484023","https://openalex.org/W4200391368","https://openalex.org/W2388221044","https://openalex.org/W3117064361","https://openalex.org/W2984236338","https://openalex.org/W2619213283"],"abstract_inverted_index":{"For":[0],"research":[1],"related":[2],"to":[3,24],"field":[4],"programmable":[5],"gate":[6],"arrays":[7],"(FPGAs),":[8],"various":[9],"FPGA":[10,18,40,44,57,64],"game":[11,19,41],"solvers":[12],"have":[13],"been":[14],"developed":[15],"recently.":[16],"The":[17,53],"solver":[20],"can":[21],"achieve":[22],"up":[23],"1,000":[25],"times":[26,73],"faster":[27],"processing":[28],"speeds":[29],"than":[30,75],"processor-based":[31],"operations.":[32],"This":[33],"paper":[34],"presents":[35],"one":[36],"development":[37],"of":[38,55,77],"such":[39],"solvers:":[42],"an":[43,63],"Trax":[45,58],"Solver":[46,59],"based":[47,79],"on":[48,62,81],"a":[49,82],"neural":[50],"network":[51],"design.":[52],"speed":[54],"the":[56],"operations":[60],"implemented":[61],"(Arria":[65],"II":[66],"GX;":[67],"Altera":[68],"Corp.)":[69],"is":[70],"over":[71],"60":[72],"greater":[74],"operation":[76],"C++":[78],"software":[80],"personal":[83],"computer":[84],"(Vostro":[85],"460;":[86],"Dell":[87],"Inc.).":[88]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}