{"id":"https://openalex.org/W2038432615","doi":"https://doi.org/10.1109/fpt.2013.6718380","title":"Design and optimization of heterogeneous tree-based FPGA using 3D technology","display_name":"Design and optimization of heterogeneous tree-based FPGA using 3D technology","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2038432615","doi":"https://doi.org/10.1109/fpt.2013.6718380","mag":"2038432615"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2013.6718380","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718380","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044271464","display_name":"Vinod Pangracious","orcid":"https://orcid.org/0000-0002-4240-6610"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Vinod Pangracious","raw_affiliation_strings":["LIP6-Universit\u00e9 Pierre et Marie Curie, France","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIP6-Universit\u00e9 Pierre et Marie Curie, France","institution_ids":["https://openalex.org/I39804081"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108405631","display_name":"Habib Mehrez","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Habib Mehrez","raw_affiliation_strings":["LIP6-Universit\u00e9 Pierre et Marie Curie, France","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIP6-Universit\u00e9 Pierre et Marie Curie, France","institution_ids":["https://openalex.org/I39804081"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111822030","display_name":"Zied Marrakchi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zied Marrakchi","raw_affiliation_strings":["FLEXRAS Technologies Paris, France","Flexras Technologies (France)","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"FLEXRAS Technologies Paris, France","institution_ids":[]},{"raw_affiliation_string":"Flexras Technologies (France)","institution_ids":[]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10159773,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2008","issue":null,"first_page":"334","last_page":"337"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8110065460205078},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6587752103805542},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6248577237129211},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6175705194473267},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5144484043121338},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5113232135772705},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49175360798835754},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.45848697423934937},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4556882083415985},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.43581312894821167},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3790851831436157},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.34327489137649536},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32128506898880005},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.27701035141944885},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2178567349910736},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.0987042784690857},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06986305117607117}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8110065460205078},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6587752103805542},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6248577237129211},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6175705194473267},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5144484043121338},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5113232135772705},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49175360798835754},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.45848697423934937},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4556882083415985},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.43581312894821167},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3790851831436157},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.34327489137649536},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32128506898880005},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.27701035141944885},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2178567349910736},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.0987042784690857},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06986305117607117},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2013.6718380","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718380","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01372833v1","is_oa":false,"landing_page_url":"https://hal.science/hal-01372833","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"FPT 2013 - International Conference on Field-Programmable Technology, Dec 2013, Kyoto, Japan. pp.334--337, ⟨10.1109/FPT.2013.6718380⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8700000047683716,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1581887721","https://openalex.org/W1830708738","https://openalex.org/W2005226599","https://openalex.org/W2047199967","https://openalex.org/W2070608594","https://openalex.org/W2132668926","https://openalex.org/W2133712953","https://openalex.org/W2157890680"],"related_works":["https://openalex.org/W2016970881","https://openalex.org/W1990828594","https://openalex.org/W2333804548","https://openalex.org/W2183559057","https://openalex.org/W4229881013","https://openalex.org/W3093450488","https://openalex.org/W8358306","https://openalex.org/W3163301441","https://openalex.org/W2027159884","https://openalex.org/W2526362253"],"abstract_inverted_index":{"The":[0],"CMOS":[1],"technology":[2],"scaling":[3],"has":[4],"greatly":[5],"improved":[6],"the":[7,22,32,50,80],"overall":[8],"performance":[9,23],"and":[10,29,83,91],"density":[11],"of":[12],"Field":[13],"Programmable":[14],"Gate":[15],"Arrays":[16],"(FPGAs).":[17],"However,":[18],"when":[19],"looking":[20],"at":[21],"metrics":[24],"such":[25],"as":[26],"speed,":[27,88],"area":[28,90],"power":[30,92],"consumption,":[31],"gap":[33],"is":[34],"generally":[35],"very":[36],"wide":[37],"for":[38],"FPGAs":[39],"compared":[40],"to":[41,49,65,86],"application":[42],"specific":[43],"integrated":[44],"circuits":[45],"(ASICs)":[46],"mainly":[47],"due":[48],"programmable":[51],"interconnect":[52,89],"overhead.":[53],"We":[54,78],"propose":[55],"a":[56,73],"3-dimensional":[57],"(3D)":[58],"design":[59,63,82],"methodology":[60,85],"using":[61,94],"horizontal":[62],"partitioning":[64],"vertically":[66],"stack":[67],"heterogeneous":[68],"FPGA":[69,76],"designs":[70],"based":[71],"on":[72],"Tree-based":[74],"multilevel":[75],"architecture.":[77],"describe":[79],"3D":[81,96],"optimization":[84],"improve":[87],"consumption":[93],"Tezzaron's":[95],"stacking":[97],"technology.":[98]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}