{"id":"https://openalex.org/W1980921996","doi":"https://doi.org/10.1109/fpt.2013.6718363","title":"Automated multi-device placement, I/O voltage supply assignment, and pin assignment in circuit board design","display_name":"Automated multi-device placement, I/O voltage supply assignment, and pin assignment in circuit board design","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W1980921996","doi":"https://doi.org/10.1109/fpt.2013.6718363","mag":"1980921996"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2013.6718363","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718363","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037031468","display_name":"Daniel P. Seemuth","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Daniel P. Seemuth","raw_affiliation_strings":["Electrical and Computer Engineering University of Wisconsin - Madison Madison, WI","Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering University of Wisconsin - Madison Madison, WI","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061323191","display_name":"Katherine Morrow","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Katherine Morrow","raw_affiliation_strings":["Electrical and Computer Engineering University of Wisconsin - Madison Madison, WI","Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering University of Wisconsin - Madison Madison, WI","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5037031468"],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":0.4729,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67300043,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"262","last_page":"269"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.673976719379425},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.6719344854354858},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6604683995246887},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.6446601748466492},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6156471967697144},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5712549090385437},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5450937151908875},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.507731556892395},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4762287735939026},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.4465562403202057},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.43174049258232117},{"id":"https://openalex.org/keywords/engineering-design-process","display_name":"Engineering design process","score":0.4313928186893463},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3477799892425537},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1792963445186615},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13029980659484863}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.673976719379425},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.6719344854354858},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6604683995246887},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.6446601748466492},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6156471967697144},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5712549090385437},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5450937151908875},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.507731556892395},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4762287735939026},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.4465562403202057},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.43174049258232117},{"id":"https://openalex.org/C34972735","wikidata":"https://www.wikidata.org/wiki/Q2920267","display_name":"Engineering design process","level":2,"score":0.4313928186893463},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3477799892425537},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1792963445186615},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13029980659484863},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2013.6718363","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718363","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W13759931","https://openalex.org/W1505317030","https://openalex.org/W1568614804","https://openalex.org/W1969208860","https://openalex.org/W2114946353","https://openalex.org/W2139637699","https://openalex.org/W2275304190","https://openalex.org/W6600540968"],"related_works":["https://openalex.org/W4387303494","https://openalex.org/W2076876796","https://openalex.org/W2359669063","https://openalex.org/W3163908127","https://openalex.org/W2391956704","https://openalex.org/W2393271092","https://openalex.org/W4384080919","https://openalex.org/W2546805501","https://openalex.org/W2317119406","https://openalex.org/W2352564925"],"abstract_inverted_index":{"Embedded":[0],"systems":[1,21,217],"often":[2,29],"contain":[3],"many":[4],"components,":[5],"some":[6],"with":[7,218],"multiple":[8,219],"Field":[9],"Programmable":[10],"Gate":[11],"Arrays":[12],"(FPGAs).":[13],"Designing":[14],"Printed":[15],"Circuit":[16],"Boards":[17],"(PCBs)":[18],"for":[19,74,202],"these":[20],"can":[22,183],"be":[23,71,211],"a":[24,56,86,105,147],"complex":[25],"process":[26],"that":[27,197],"is":[28],"tedious,":[30],"error-prone,":[31],"and":[32,44,68,77,95,122,136,178,182,191],"time-intensive.":[33],"Existing":[34],"computer-aided":[35],"design":[36,62,93,99,179,189,204],"tools":[37],"require":[38],"designers":[39,215],"to":[40,91,140,150,164,185],"manually":[41],"insert":[42],"components":[43,121],"explicitly":[45],"define":[46],"the":[47,53,98,120,125,208],"connections":[48],"between":[49,117],"every":[50],"component":[51,130],"on":[52],"PCB":[54,61],"-":[55],"cumbersome":[57],"process.":[58],"A":[59],"fast":[60],"framework":[63,90,127,169,209],"requiring":[64],"reduced":[65],"designer":[66],"time":[67,190],"effort":[69],"would":[70],"particularly":[72],"advantageous":[73],"rapid":[75,176],"prototyping":[76,177],"short":[78],"production":[79],"run":[80],"PCBs.":[81],"Therefore,":[82],"this":[83],"paper":[84],"proposes":[85],"novel,":[87],"freely-available":[88],"open-source":[89],"capture":[92],"intent":[94],"automatically":[96,128],"implement":[97],"details.":[100],"Designers":[101],"express":[102],"connectivity":[103],"at":[104],"higher":[106],"level":[107],"of":[108,216,224],"abstraction":[109],"than":[110],"enumerating":[111],"or":[112],"drawing":[113],"each":[114],"individual":[115],"trace":[116,142,152],"components.":[118],"Given":[119],"connection":[123],"requirements,":[124,205],"proposed":[126,168],"generates":[129],"placements,":[131],"I/O":[132],"voltage":[133],"supply":[134],"assignments,":[135],"FPGA":[137,158],"pin":[138],"assignments":[139],"minimize":[141],"length.":[143],"We":[144,195],"also":[145],"propose":[146],"novel":[148],"method":[149],"improve":[151],"length":[153],"estimations":[154],"during":[155],"placement,":[156],"before":[157],"pins":[159],"have":[160],"actually":[161],"been":[162],"assigned":[163],"those":[165],"connections.":[166],"The":[167],"quickly":[170],"explores":[171],"large":[172,222],"solution":[173],"spaces,":[174],"enabling":[175],"space":[180],"exploration,":[181],"lead":[184],"lower":[186],"costs":[187],"in":[188],"other":[192],"non-recurring":[193],"expenses.":[194],"demonstrate":[196],"it":[198],"produces":[199],"favorable":[200],"results":[201],"various":[203],"which":[206],"suggests":[207],"will":[210],"especially":[212],"appreciated":[213],"by":[214],"FPGAs":[220],"having":[221],"numbers":[223],"flexible":[225],"pins.":[226]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}