{"id":"https://openalex.org/W2057470132","doi":"https://doi.org/10.1109/fpt.2013.6718362","title":"Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting","display_name":"Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2057470132","doi":"https://doi.org/10.1109/fpt.2013.6718362","mag":"2057470132"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2013.6718362","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718362","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083017828","display_name":"Zhenyu Guan","orcid":"https://orcid.org/0000-0002-3959-338X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Zhenyu Guan","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Justin S. J. Wong","raw_affiliation_strings":["Imperial College London, London, London, GB","Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, London, GB","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056146508","display_name":"Sumanta Chaudhuri","orcid":"https://orcid.org/0000-0002-8337-079X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Sumanta Chaudhuri","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George Constantinides","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, UK","Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Imperial College London, London, London, GB","Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, London, GB","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.4698,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.69448885,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"26","issue":null,"first_page":"254","last_page":"261"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.830213189125061},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.7598618268966675},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.7340379953384399},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6910579204559326},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6880024671554565},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.6107500791549683},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5415525436401367},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.48834487795829773},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.44416919350624084},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4334806799888611},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34527987241744995},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3355923891067505},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.2946803569793701},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.287095308303833},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2605610489845276},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08721268177032471}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.830213189125061},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.7598618268966675},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.7340379953384399},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6910579204559326},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6880024671554565},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.6107500791549683},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5415525436401367},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.48834487795829773},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.44416919350624084},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4334806799888611},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34527987241744995},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3355923891067505},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.2946803569793701},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.287095308303833},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2605610489845276},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08721268177032471},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2013.6718362","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718362","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-04516507v1","is_oa":false,"landing_page_url":"https://telecom-paris.hal.science/hal-04516507","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT), Dec 2013, Kyoto, Japan. pp.254-261, ⟨10.1109/FPT.2013.6718362⟩","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5}],"awards":[{"id":"https://openalex.org/G3502913390","display_name":null,"funder_award_id":"EP/H013784/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W2096227207","https://openalex.org/W2096581954","https://openalex.org/W2103156522","https://openalex.org/W2108165851","https://openalex.org/W2117648153","https://openalex.org/W2120116751","https://openalex.org/W2126382422","https://openalex.org/W2126460975","https://openalex.org/W2154446814","https://openalex.org/W2155142975","https://openalex.org/W2156041594","https://openalex.org/W2158101706","https://openalex.org/W2178225970","https://openalex.org/W4251154776","https://openalex.org/W4254506919"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W2145535176","https://openalex.org/W2158805860","https://openalex.org/W4229446324","https://openalex.org/W1570180536","https://openalex.org/W2117925677","https://openalex.org/W3140640533","https://openalex.org/W2110367374","https://openalex.org/W1804063983","https://openalex.org/W2134944363"],"abstract_inverted_index":{"Aggressive":[0],"transistor":[1],"scaling":[2],"will":[3],"soon":[4],"lead":[5],"us":[6],"to":[7,34,46,67],"the":[8,19,40,69,75],"physical":[9],"upper-bound":[10],"of":[11,22,39,42,74,96,119],"process":[12,16,47],"technology,":[13],"where":[14],"stochastic":[15],"variability":[17,44,95],"dominates":[18],"timing":[20,117],"performance":[21],"FPGA":[23,56,80],"components.":[24],"In":[25],"this":[26],"paper,":[27],"a":[28,93,114],"variation-aware":[29,108],"partial-rerouting":[30,83],"method":[31,77,84],"is":[32,59,65,101],"proposed":[33,76],"mitigate":[35],"and":[36,64,71,100],"take":[37],"advantage":[38],"effect":[41],"delay":[43,53,91,94],"due":[45],"variation.":[48],"The":[49],"variation":[50,135],"in":[51,88],"logic":[52],"across":[54],"each":[55],"(variation":[57],"map)":[58],"measured":[60],"on":[61,78],"commercial":[62],"FPGAs":[63,132],"used":[66],"assess":[68],"effectiveness":[70],"potential":[72],"gain":[73,118],"current":[79],"architectures.":[81],"Our":[82],"achieved":[85],"5.25%":[86],"improvement":[87],"critical":[89],"path":[90],"under":[92],"\u03c3/\u03bc":[97],"=":[98],"0.3,":[99],"considerably":[102],"less":[103],"time":[104,126],"consuming":[105],"than":[106],"using":[107],"full":[109],"chipwise":[110],"routing,":[111],"which":[112],"gave":[113],"slightly":[115],"better":[116],"6.41%":[120],"but":[121],"requires":[122],"8x":[123],"more":[124],"execution":[125],"when":[127],"optimising":[128],"for":[129],"100":[130],"target":[131],"with":[133],"unique":[134],"maps.":[136]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}