{"id":"https://openalex.org/W2025737663","doi":"https://doi.org/10.1109/fpt.2013.6718346","title":"Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA","display_name":"Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2025737663","doi":"https://doi.org/10.1109/fpt.2013.6718346","mag":"2025737663"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2013.6718346","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718346","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066019284","display_name":"Xitian Fan","orcid":"https://orcid.org/0000-0001-8698-6584"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xitian Fan","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101349755","display_name":"Chenlu Wu","orcid":"https://orcid.org/0009-0004-4846-1540"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenlu Wu","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100694034","display_name":"Wei Cao","orcid":"https://orcid.org/0000-0003-0339-7093"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Cao","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103281733","display_name":"Xuegong Zhou","orcid":"https://orcid.org/0000-0003-4178-4094"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuegong Zhou","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101624040","display_name":"Shengye Wang","orcid":"https://orcid.org/0000-0003-3723-6853"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shengye Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002732486","display_name":"Lingli Wang","orcid":"https://orcid.org/0000-0002-0579-3527"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Lab. of ASIC & Syst. Fudan Univ., Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5066019284"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"],"apc_list":null,"apc_paid":null,"fwci":2.1773,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.89171806,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"152","last_page":"159"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10627","display_name":"Advanced Image and Video Retrieval Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10627","display_name":"Advanced Image and Video Retrieval Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10191","display_name":"Robotics and Sensor-Based Localization","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8332571387290955},{"id":"https://openalex.org/keywords/frame-rate","display_name":"Frame rate","score":0.7411391735076904},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7324161529541016},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5628080368041992},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.5564056634902954},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5309934616088867},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4974687397480011},{"id":"https://openalex.org/keywords/video-graphics-array","display_name":"Video Graphics Array","score":0.4923003911972046},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4775274991989136},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.45913153886795044},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4542740285396576},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44914960861206055},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3400474190711975},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.18015512824058533},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1715831458568573},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11196908354759216},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.09070780873298645}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8332571387290955},{"id":"https://openalex.org/C3261483","wikidata":"https://www.wikidata.org/wiki/Q119565","display_name":"Frame rate","level":2,"score":0.7411391735076904},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7324161529541016},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5628080368041992},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.5564056634902954},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5309934616088867},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4974687397480011},{"id":"https://openalex.org/C139983466","wikidata":"https://www.wikidata.org/wiki/Q17194","display_name":"Video Graphics Array","level":3,"score":0.4923003911972046},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4775274991989136},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.45913153886795044},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4542740285396576},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44914960861206055},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3400474190711975},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.18015512824058533},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1715831458568573},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11196908354759216},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.09070780873298645},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2013.6718346","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718346","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W62482549","https://openalex.org/W1982935629","https://openalex.org/W1996395672","https://openalex.org/W2002303850","https://openalex.org/W2066679163","https://openalex.org/W2100677669","https://openalex.org/W2107186825","https://openalex.org/W2118843251","https://openalex.org/W2119605622","https://openalex.org/W2137584778","https://openalex.org/W2140273727","https://openalex.org/W2150440820","https://openalex.org/W2151014835","https://openalex.org/W2151103935","https://openalex.org/W2152724437","https://openalex.org/W2156409111","https://openalex.org/W2158059210","https://openalex.org/W2164713242","https://openalex.org/W2165647442","https://openalex.org/W2177274842","https://openalex.org/W3139995341","https://openalex.org/W6602521380","https://openalex.org/W6680270604","https://openalex.org/W6682431704"],"related_works":["https://openalex.org/W2128437995","https://openalex.org/W2360644583","https://openalex.org/W2383534223","https://openalex.org/W2086672486","https://openalex.org/W2348524279","https://openalex.org/W2776198954","https://openalex.org/W2575964431","https://openalex.org/W2544255433","https://openalex.org/W2141277095","https://openalex.org/W2980331305"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,35,52,164,167],"high":[4,22],"performance":[5],"hardware":[6,27,127],"architecture":[7,28,128],"of":[8,123,160,178],"Speeded":[9],"Up":[10],"Robust":[11],"Features":[12],"(SURF)":[13],"algorithm":[14],"based":[15],"on":[16,131,163,182],"OpenSURF.":[17],"In":[18,82],"order":[19,105],"to":[20,41,76,98,106],"achieve":[21],"processing":[23],"frame":[24,141,158,176],"rate,":[25],"the":[26,54,78,93,119,174,179],"is":[29,39,68,96,129,155],"designed":[30],"with":[31,135,166],"several":[32],"characteristics.":[33],"Firstly,":[34],"sliding":[36],"window":[37],"method":[38],"proposed":[40,69],"extract":[42],"feature":[43,58],"points":[44],"in":[45,57,70,100,104,111],"parallel":[46],"at":[47],"selected":[48],"scale":[49],"levels.":[50],"As":[51],"result,":[53],"time":[55,122],"cost":[56],"extraction":[59],"can":[60,147],"be":[61],"greatly":[62],"reduced.":[63],"Secondly,":[64],"data":[65,109],"reuse":[66],"strategy":[67],"orientation":[71],"generation":[72,75],"and":[73,86,138,171],"descriptor":[74],"reduce":[77,118],"memory":[79,102],"access":[80],"times.":[81],"this":[83],"way,":[84],"3.87x":[85],"2.25X":[87],"speedup":[88],"are":[89],"achieved":[90],"respectively.":[91],"Thirdly,":[92],"integral":[94],"image":[95,146],"segmented":[97],"buffer":[99],"different":[101],"blocks":[103],"support":[107],"multiple":[108],"accessing":[110],"one":[112],"clock":[113],"cycle,":[114],"which":[115,154],"will":[116],"further":[117],"whole":[120],"calculating":[121],"our":[124],"implementation.":[125],"The":[126],"implemented":[130],"an":[132],"XC6VSX475T":[133],"FPGA":[134],"156":[136],"MHz":[137],"its":[139],"maximal":[140],"rate":[142,159,177],"for":[143],"VGA":[144],"format":[145],"reach":[148],"356":[149],"frames":[150],"per":[151],"second":[152],"(fps),":[153],"6.25":[156],"times":[157,173],"OpenSURF":[161],"running":[162],"server":[165],"Xeon":[168],"5650":[169],"processor,":[170],"6":[172],"reported":[175],"recent":[180],"implementation":[181],"three":[183],"Vritex4":[184],"FPGAs":[185],"[8].":[186]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
