{"id":"https://openalex.org/W2038399995","doi":"https://doi.org/10.1109/fpt.2013.6718329","title":"Debugging processors with advanced features by reprogramming LUTs on FPGA","display_name":"Debugging processors with advanced features by reprogramming LUTs on FPGA","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2038399995","doi":"https://doi.org/10.1109/fpt.2013.6718329","mag":"2038399995"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2013.6718329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055047977","display_name":"Satoshi Jo","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]},{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Satoshi Jo","raw_affiliation_strings":["Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, JAPAN","[Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, JAPAN","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]},{"raw_affiliation_string":"[Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan]","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053471252","display_name":"Amir Masoud Gharehbaghi","orcid":"https://orcid.org/0000-0002-0451-221X"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]},{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Amir Masoud Gharehbaghi","raw_affiliation_strings":["Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, JAPAN","[Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, JAPAN","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]},{"raw_affiliation_string":"[Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan]","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054079223","display_name":"Takeshi Matsumoto","orcid":"https://orcid.org/0000-0002-1517-0761"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takeshi Matsumoto","raw_affiliation_strings":["VLSI Design and Education Center, The University of Tokyoz, Tokyo, JAPAN","[VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, The University of Tokyoz, Tokyo, JAPAN","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"[VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan]","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["VLSI Design and Education Center, The University of Tokyoz, Tokyo, JAPAN","[VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, The University of Tokyoz, Tokyo, JAPAN","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"[VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan]","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5055047977"],"corresponding_institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.7251,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.72566576,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"50","last_page":"57"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8551446199417114},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8340872526168823},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5529789328575134},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5347563028335571},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5132825374603271},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4183543622493744},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4141487181186676},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41152051091194153},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34270602464675903},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.332966685295105},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3317577540874481},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.277363657951355},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12777894735336304}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8551446199417114},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8340872526168823},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5529789328575134},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5347563028335571},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5132825374603271},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4183543622493744},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4141487181186676},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41152051091194153},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34270602464675903},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.332966685295105},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3317577540874481},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.277363657951355},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12777894735336304},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2013.6718329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1503377936","https://openalex.org/W1528837436","https://openalex.org/W1741528175","https://openalex.org/W1965646191","https://openalex.org/W1983614217","https://openalex.org/W1985685974","https://openalex.org/W2047904776","https://openalex.org/W2060407451","https://openalex.org/W2123503453","https://openalex.org/W2140132043","https://openalex.org/W2142726962","https://openalex.org/W2163601989","https://openalex.org/W2178304595","https://openalex.org/W2914069437","https://openalex.org/W3151473321","https://openalex.org/W4253064847","https://openalex.org/W6630097642","https://openalex.org/W6665802101","https://openalex.org/W7047819290"],"related_works":["https://openalex.org/W4321442002","https://openalex.org/W2015265939","https://openalex.org/W2284072287","https://openalex.org/W2611067230","https://openalex.org/W2480201319","https://openalex.org/W2387706296","https://openalex.org/W2155788121","https://openalex.org/W4235469518","https://openalex.org/W362492756","https://openalex.org/W2890345561"],"abstract_inverted_index":{"In":[0,94],"this":[1],"paper,":[2],"we":[3,98,114,129,172],"propose":[4],"an":[5,157],"automated":[6],"method":[7,23,190,235],"for":[8,66],"debugging":[9,33,119],"and":[10,32,34,120,153,164,202],"rectification":[11,121],"of":[12,42,78,91,161,213,233],"logical":[13],"bugs":[14,36,55,85,238],"in":[15,108,118,239],"processors":[16,68,244],"that":[17,113,191],"are":[18],"implemented":[19],"on":[20,26],"FPGAs.":[21],"Our":[22],"is":[24,81,126,147,185],"based":[25],"preserving":[27],"the":[28,40,48,54,76,79,84,89,92,95,109,133,162,176,180,193],"current":[29],"circuit":[30,80],"topology,":[31],"rectifying":[35],"by":[37,149,187,205,236],"only":[38],"changing":[39],"contents":[41],"LUTs,":[43],"without":[44],"any":[45],"modification":[46],"to":[47,70,106,131,142,174],"wiring.":[49],"As":[50,75],"a":[51,124,188,196,246],"result,":[52],"correcting":[53,83,237],"does":[56,86],"not":[57,87],"require":[58],"re-synthesis,":[59],"which":[60],"can":[61,115],"be":[62],"very":[63],"time":[64],"consuming":[65],"complex":[67,241],"due":[69],"possible":[71],"timing":[72,247],"closure":[73],"problems.":[74],"topology":[77],"preserved,":[82],"affect":[88],"timings":[90],"circuit.":[93],"design":[96],"phase,":[97],"may":[99],"add":[100],"additional":[101,104],"LUTs":[102,107],"or":[103],"inputs":[105],"original":[110],"circuit,":[111],"so":[112],"use":[116],"them":[117],"phase.":[122],"After":[123],"bug":[125],"found,":[127],"first":[128],"try":[130,173],"identify":[132],"candidate":[134],"signals":[135],"as":[136,138,195,229,231],"well":[137,230],"their":[139,144],"required":[140],"changes":[141],"correct":[143],"behavior.":[145],"This":[146,184],"achieved":[148],"using":[150],"symbolic":[151],"simulation":[152],"equivalence":[154],"checking":[155],"between":[156],"instruction-set":[158],"architecture":[159],"model":[160,167],"processor":[163],"its":[165],"erroneous":[166],"at":[168],"micro-architecture":[169],"level.":[170],"Then,":[171],"map":[175],"corrected":[177],"functionality":[178],"into":[179],"existing":[181],"LUT":[182],"topology.":[183],"realized":[186],"novel":[189],"formulates":[192],"problem":[194],"QBF":[197,214],"(Quantified":[198],"Boolean":[199],"Formula)":[200],"problem,":[201],"solves":[203],"it":[204],"repeatedly":[206],"applying":[207],"normal":[208],"SAT":[209],"solvers":[210,215],"incrementally":[211],"instead":[212],"utilizing":[216],"ideas":[217],"from":[218],"CEGAR":[219],"(Counter":[220],"Example":[221],"Guided":[222],"Abstraction":[223],"Refinement)":[224],"paradigm.":[225],"We":[226],"show":[227],"effectiveness":[228],"efficiency":[232],"our":[234],"two":[240],"out-of-order":[242],"superscalar":[243],"with":[245],"error":[248],"recovery":[249],"mechanism.":[250]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}