{"id":"https://openalex.org/W2070101640","doi":"https://doi.org/10.1109/fpt.2013.6718328","title":"A case for hardened multiplexers in FPGAs","display_name":"A case for hardened multiplexers in FPGAs","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2070101640","doi":"https://doi.org/10.1109/fpt.2013.6718328","mag":"2070101640"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2013.6718328","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718328","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109210828","display_name":"S. Alexander Chin","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S. Alexander Chin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada#TAB#","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102812429","display_name":"Jason H. Anderson","orcid":"https://orcid.org/0000-0001-9083-6853"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jason H. Anderson","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada#TAB#","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.9602,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.79201769,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"42","last_page":"49"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.8019023537635803},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7105727791786194},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6780840158462524},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6674493551254272},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5987551212310791},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.562156081199646},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5448697209358215},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5037888884544373},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4851592183113098},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4845639765262604},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.48274320363998413},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.45072507858276367},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4430466294288635},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4378443956375122},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38588711619377136},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35428187251091003},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3273402452468872},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.14377203583717346},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1219353973865509},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09982597827911377},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09033000469207764}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.8019023537635803},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7105727791786194},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6780840158462524},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6674493551254272},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5987551212310791},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.562156081199646},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5448697209358215},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5037888884544373},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4851592183113098},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4845639765262604},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.48274320363998413},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.45072507858276367},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4430466294288635},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4378443956375122},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38588711619377136},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35428187251091003},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3273402452468872},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.14377203583717346},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1219353973865509},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09982597827911377},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09033000469207764},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2013.6718328","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718328","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.656.8992","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.656.8992","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://janders.eecg.toronto.edu/pdfs/xan.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1972355764","https://openalex.org/W1977850862","https://openalex.org/W2018055497","https://openalex.org/W2057807751","https://openalex.org/W2100465945","https://openalex.org/W2100955320","https://openalex.org/W2112037954","https://openalex.org/W2113645429","https://openalex.org/W2120397377","https://openalex.org/W2120569261","https://openalex.org/W2123192957","https://openalex.org/W2133287836","https://openalex.org/W2138383740","https://openalex.org/W2139026138","https://openalex.org/W2139637699","https://openalex.org/W2152001402","https://openalex.org/W2164340799","https://openalex.org/W3143290261","https://openalex.org/W4249037642","https://openalex.org/W6675636599","https://openalex.org/W6680409802","https://openalex.org/W6680692090","https://openalex.org/W6682862348"],"related_works":["https://openalex.org/W2003435315","https://openalex.org/W2135636985","https://openalex.org/W2139569078","https://openalex.org/W4379115868","https://openalex.org/W4252227487","https://openalex.org/W2063686821","https://openalex.org/W4252906329","https://openalex.org/W2171679639","https://openalex.org/W2151927748","https://openalex.org/W2139206565"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,6,13,43],"case":[4],"for":[5],"hybrid":[7,62,74],"configurable":[8,63,75,135],"logic":[9,25,52,64,76,136],"block":[10,65,77,137],"that":[11,35,102],"contains":[12],"mixture":[14],"of":[15,23,46],"LUTs":[16],"and":[17,27,66,70,93,114,116,128,139],"hardened":[18],"multiplexers":[19],"towards":[20],"the":[21,37,47,50,60],"goal":[22],"higher":[24],"density":[26],"area":[28,111,124],"reduction.":[29],"Technology":[30],"mapping":[31,132],"optimizations,":[32],"called":[33],"MuxMap,":[34],"target":[36],"proposed":[38],"architecture":[39],"are":[40,83],"implemented":[41],"using":[42],"modified":[44],"version":[45],"mapper":[48,105],"in":[49,120],"ABC":[51,121],"synthesis":[53,97],"tool.":[54],"VPR":[55],"is":[56],"used":[57],"to":[58],"model":[59],"new":[61],"verify":[67],"post":[68,112,126],"place":[69,113,127],"route":[71,115,129],"implementation.":[72],"Multiple":[73],"architectures":[78],"with":[79,89,117],"varying":[80],"MUX:LUT":[81],"ratios":[82],"evaluated":[84],"across":[85],"three":[86],"benchmark":[87],"suites":[88],"both":[90],"Quartus":[91],"II":[92],"Odin-II":[94],"front-end":[95],"RTL":[96],"tools.":[98],"Experimentally,":[99],"we":[100,107],"show":[101],"without":[103],"any":[104],"optimizations":[106,119],"naturally":[108],"save":[109],"~4%":[110],"MuxMap":[118],"yielding":[122],"~6%":[123],"reduction":[125],"while":[130],"maintaining":[131],"depth,":[133],"overall":[134],"count,":[138],"routing":[140],"demand.":[141]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
