{"id":"https://openalex.org/W2071754498","doi":"https://doi.org/10.1109/fpt.2013.6718319","title":"Reconfigurable chip advantage compared with GPGPU from the compiler perspective","display_name":"Reconfigurable chip advantage compared with GPGPU from the compiler perspective","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2071754498","doi":"https://doi.org/10.1109/fpt.2013.6718319","mag":"2071754498"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2013.6718319","is_oa":true,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718319","pdf_url":"https://ieeexplore.ieee.org/ielx7/6712172/6718311/06718319.pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://ieeexplore.ieee.org/ielx7/6712172/6718311/06718319.pdf","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100885113","display_name":"Kazutoshi Wakabayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Kazutoshi Wakabayashi","raw_affiliation_strings":["NEC Corporation","NEC (Japan), Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"NEC Corporation","institution_ids":[]},{"raw_affiliation_string":"NEC (Japan), Tokyo, Japan","institution_ids":["https://openalex.org/I118347220"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5100885113"],"corresponding_institution_ids":["https://openalex.org/I118347220"],"apc_list":null,"apc_paid":null,"fwci":0.6304,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.70565128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"2","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9757999777793884,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9028000235557556,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8573418855667114},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8462221622467041},{"id":"https://openalex.org/keywords/general-purpose-computing-on-graphics-processing-units","display_name":"General-purpose computing on graphics processing units","score":0.8382595777511597},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8191026449203491},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7273353338241577},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4773143231868744},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4250975251197815},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35794639587402344},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3274874687194824},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.2378171682357788},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10485005378723145}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8573418855667114},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8462221622467041},{"id":"https://openalex.org/C50630238","wikidata":"https://www.wikidata.org/wiki/Q971505","display_name":"General-purpose computing on graphics processing units","level":3,"score":0.8382595777511597},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8191026449203491},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7273353338241577},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4773143231868744},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4250975251197815},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35794639587402344},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3274874687194824},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.2378171682357788},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10485005378723145}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2013.6718319","is_oa":true,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718319","pdf_url":"https://ieeexplore.ieee.org/ielx7/6712172/6718311/06718319.pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1109/fpt.2013.6718319","is_oa":true,"landing_page_url":"https://doi.org/10.1109/fpt.2013.6718319","pdf_url":"https://ieeexplore.ieee.org/ielx7/6712172/6718311/06718319.pdf","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Field-Programmable Technology (FPT)","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2071754498.pdf","grobid_xml":"https://content.openalex.org/works/W2071754498.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2002505081","https://openalex.org/W2083681681","https://openalex.org/W2577630842","https://openalex.org/W3146558274","https://openalex.org/W1172579163","https://openalex.org/W1488300410","https://openalex.org/W2138790427","https://openalex.org/W4246454774","https://openalex.org/W2162051035","https://openalex.org/W1995144992"],"abstract_inverted_index":{"This":[0],"presentation":[1],"discusses":[2],"how":[3],"FPGA":[4],"or":[5],"coarse":[6,34],"grained":[7,32,35],"reconfigurable":[8,36],"processor":[9],"is":[10],"superior":[11],"to":[12,63],"CPU/GPGPU":[13],"from":[14],"the":[15,24,64],"view":[16],"point":[17],"of":[18,27,46,68],"C":[19],"compiler.":[20],"Initially,":[21],"we":[22,42],"introduce":[23],"architectural":[25],"characteristic":[26],"CPU,":[28],"GPGPU":[29,61],"and":[30,33,53],"fine":[31],"process":[37],"with":[38,51],"FSM+Datapath":[39],"model.":[40],"Then,":[41],"explain":[43],"what":[44],"kind":[45],"applications":[47],"can":[48],"be":[49],"accelerated":[50],"\"FPGA":[52],"C-based":[54],"High":[55],"Level":[56],"Synthesis":[57],"Tool\"":[58],"better":[59],"than":[60],"according":[62],"compiler":[65,69],"techniques":[66],"(freedom":[67],"parallelization).":[70]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}