{"id":"https://openalex.org/W2017271079","doi":"https://doi.org/10.1109/fpt.2012.6412140","title":"Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew","display_name":"Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew","publication_year":2012,"publication_date":"2012-12-01","ids":{"openalex":"https://openalex.org/W2017271079","doi":"https://doi.org/10.1109/fpt.2012.6412140","mag":"2017271079"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2012.6412140","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2012.6412140","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084837030","display_name":"Alexander Brant","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Alexander Brant","raw_affiliation_strings":["Dept. of ECE, University of British Columbia, Vancouver, Canada","[Department of ECE, University of British Columbia, Vancouver, Canada]"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"[Department of ECE, University of British Columbia, Vancouver, Canada]","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005226229","display_name":"Ameer Abdelhadi","orcid":"https://orcid.org/0000-0003-4683-8901"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Ameer Abdelhadi","raw_affiliation_strings":["Dept. of ECE, University of British Columbia, Vancouver, Canada","[Department of ECE, University of British Columbia, Vancouver, Canada]"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"[Department of ECE, University of British Columbia, Vancouver, Canada]","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038077890","display_name":"Aaron Severance","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Aaron Severance","raw_affiliation_strings":["Dept. of ECE, University of British Columbia, Vancouver, Canada","[Department of ECE, University of British Columbia, Vancouver, Canada]"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"[Department of ECE, University of British Columbia, Vancouver, Canada]","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071113717","display_name":"Guy Lemieux","orcid":"https://orcid.org/0000-0002-7924-8695"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Guy G.F. Lemieux","raw_affiliation_strings":["Dept. of ECE, University of British Columbia, Vancouver, Canada","[Department of ECE, University of British Columbia, Vancouver, Canada]"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"[Department of ECE, University of British Columbia, Vancouver, Canada]","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5084837030"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.4503,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.81094248,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"235","last_page":"238"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7877915501594543},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.573624312877655},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.55161052942276},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5434756875038147},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47341591119766235},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4726371169090271},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4684232473373413},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.45358210802078247},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36717987060546875},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14559730887413025},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13496184349060059},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.10173103213310242}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7877915501594543},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.573624312877655},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.55161052942276},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5434756875038147},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47341591119766235},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4726371169090271},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4684232473373413},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.45358210802078247},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36717987060546875},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14559730887413025},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13496184349060059},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.10173103213310242},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2012.6412140","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2012.6412140","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1598409309","https://openalex.org/W1875554762","https://openalex.org/W2011778848","https://openalex.org/W2049960281","https://openalex.org/W2101301454","https://openalex.org/W2118482092","https://openalex.org/W2144786659","https://openalex.org/W2154555084"],"related_works":["https://openalex.org/W4247089581","https://openalex.org/W2174922170","https://openalex.org/W3006003651","https://openalex.org/W331180034","https://openalex.org/W2107880456","https://openalex.org/W1596690381","https://openalex.org/W4321517886","https://openalex.org/W4253421865","https://openalex.org/W1526416583","https://openalex.org/W2111880608"],"abstract_inverted_index":{"FPGAs":[0],"are":[1,44,125],"increasingly":[2],"being":[3],"used":[4],"to":[5,18,55,69,86,133],"implement":[6,38],"many":[7],"new":[8],"applications,":[9],"including":[10],"pipelined":[11,117,122],"processor":[12],"designs.":[13],"Designers":[14],"often":[15,35],"employ":[16],"memories":[17,57],"communicate":[19],"and":[20,32,52,58,89,127,130,162],"pass":[21],"data":[22],"between":[23,30],"these":[24,56],"pipeline":[25,71],"stages.":[26],"However,":[27],"one-cycle":[28],"communication":[29],"sender":[31],"receiver":[33],"is":[34],"required.":[36],"To":[37],"this":[39,80],"read-immediately-after-write":[40],"functionality,":[41,152],"bypass":[42,60,95],"registers":[43],"needed":[45],"by":[46],"most":[47],"FPGA":[48],"memory":[49,87,123],"blocks.":[50],"Read":[51],"write":[53,88],"latencies":[54],"the":[59,72,78,100,112,116,141,158,165,170,178],"can":[61],"limit":[62],"clock":[63,83,101,137,160],"frequencies,":[64],"or":[65],"require":[66],"extra":[67],"resources":[68,176],"further":[70,76],"bypass.":[73,118],"Instead":[74],"of":[75,92,115,121,147,155],"pipelining":[77],"bypass,":[79],"paper":[81],"applies":[82],"skew":[84,102,138],"scheduling":[85,139],"read":[90],"ports":[91],"a":[93],"simple":[94],"circuit.":[96],"We":[97],"show":[98],"that":[99],"provides":[103],"an":[104,153],"improved":[105],"F":[106,143],"<sub":[107,144],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[108,145],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">max</sub>":[109,146],"without":[110],"requiring":[111],"area":[113,131],"overhead":[114],"Many":[119],"configurations":[120],"systems":[124],"implemented,":[126],"their":[128],"speed":[129],"compared":[132],"our":[134],"design.":[135,168],"Memory":[136],"yields":[140],"best":[142,166,180],"all":[148],"techniques":[149],"which":[150],"preserve":[151],"improvement":[154],"56%":[156],"over":[157,164],"baseline":[159],"speed,":[161],"14%":[163],"conventional":[167],"Furthermore,":[169],"suggested":[171],"technique":[172],"consumes":[173],"46%":[174],"fewer":[175],"than":[177],"next":[179],"performing":[181],"technique.":[182]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}