{"id":"https://openalex.org/W2018147837","doi":"https://doi.org/10.1109/fpt.2012.6412138","title":"Introducing irregularity to routing architecture of structured ASIC for better routability","display_name":"Introducing irregularity to routing architecture of structured ASIC for better routability","publication_year":2012,"publication_date":"2012-12-01","ids":{"openalex":"https://openalex.org/W2018147837","doi":"https://doi.org/10.1109/fpt.2012.6412138","mag":"2018147837"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2012.6412138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2012.6412138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021863397","display_name":"Insup Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Insup Shin","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, Korea","Department of Electrical Engineering, KAIST, Daejeon, 305-701 Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, 305-701 Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069520131","display_name":"Donkyu Baek","orcid":"https://orcid.org/0000-0002-8056-744X"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Donkyu Baek","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, Korea","Department of Electrical Engineering, KAIST, Daejeon, 305-701 Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, 305-701 Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, Korea","Department of Electrical Engineering, KAIST, Daejeon, 305-701 Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, 305-701 Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157485424"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08767718,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"224","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.9300691485404968},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.8140867948532104},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5766478776931763},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5311017632484436},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48392635583877563},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.47360992431640625},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4460790157318115},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44351521134376526},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43697723746299744},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.43509313464164734},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.411638081073761},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.377792626619339},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32600465416908264},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.2934291958808899},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2093997299671173}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.9300691485404968},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.8140867948532104},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5766478776931763},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5311017632484436},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48392635583877563},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.47360992431640625},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4460790157318115},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44351521134376526},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43697723746299744},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.43509313464164734},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.411638081073761},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.377792626619339},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32600465416908264},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.2934291958808899},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2093997299671173},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2012.6412138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2012.6412138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.5799999833106995,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2097774291","https://openalex.org/W2109887272","https://openalex.org/W2116075993","https://openalex.org/W2139637699","https://openalex.org/W2156143104","https://openalex.org/W2157128002","https://openalex.org/W3146873982","https://openalex.org/W6680692090","https://openalex.org/W6682909919"],"related_works":["https://openalex.org/W2197466303","https://openalex.org/W4234601000","https://openalex.org/W2526362253","https://openalex.org/W2135636985","https://openalex.org/W2151236218","https://openalex.org/W1512285683","https://openalex.org/W2147419146","https://openalex.org/W2139569078","https://openalex.org/W1607849496","https://openalex.org/W2134697552"],"abstract_inverted_index":{"Imposing":[0],"regularity":[1],"presents":[2],"a":[3,40,58,76],"fundamental":[4],"limitation":[5],"to":[6,69,95,98,103,121,131],"any":[7,13],"structured":[8,28,37,73,100],"ASIC,":[9,29,38],"or":[10],"more":[11],"generally":[12],"programmable":[14,33],"logic":[15,34],"device.":[16],"It":[17],"has":[18],"been":[19],"recently":[20],"shown":[21],"that":[22],"irregularity":[23,48,65],"can":[24,49,66],"be":[25,50,67],"introduced":[26,68],"in":[27,30,32],"particular":[31,54],"elements":[35],"of":[36,47,72,82,85],"through":[39],"special":[41],"photolithography":[42],"process,":[43],"and":[44,127],"the":[45,89,114,132],"degree":[46],"customized":[51],"for":[52],"each":[53],"design":[55],"by":[56,93,111,119],"manufacturing":[57],"few":[59],"extra":[60],"masks.":[61],"We":[62],"experiment":[63],"how":[64],"routing":[70,78,87,125,128],"architecture":[71],"ASIC.":[74],"When":[75],"whole":[77],"area":[79,90],"is":[80,91,108,117],"made":[81,109],"an":[83],"array":[84],"two":[86],"architectures,":[88],"reduced":[92,118],"8%":[94],"16%":[96],"(compared":[97],"standard":[99],"ASIC)":[101],"due":[102],"less":[104],"white":[105],"space,":[106],"which":[107],"possible":[110],"improved":[112],"routability;":[113],"total":[115],"wirelength":[116],"6%":[120],"14%.":[122],"The":[123],"new":[124],"architectures":[126,133],"algorithm":[129],"specific":[130],"are":[134],"presented.":[135]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}