{"id":"https://openalex.org/W2096445089","doi":"https://doi.org/10.1109/fpt.2010.5681429","title":"Rapid prototyping tools for FPGA designs: RapidSmith","display_name":"Rapid prototyping tools for FPGA designs: RapidSmith","publication_year":2010,"publication_date":"2010-12-01","ids":{"openalex":"https://openalex.org/W2096445089","doi":"https://doi.org/10.1109/fpt.2010.5681429","mag":"2096445089"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2010.5681429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2010.5681429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087018699","display_name":"Christopher Lavin","orcid":"https://orcid.org/0000-0002-8091-0973"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher Lavin","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","institution_ids":["https://openalex.org/I100005738"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023135576","display_name":"Marc Padilla","orcid":"https://orcid.org/0000-0002-9432-6591"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Marc Padilla","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","institution_ids":["https://openalex.org/I100005738"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074917892","display_name":"Philip Lundrigan","orcid":"https://orcid.org/0000-0002-8276-4842"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Philip Lundrigan","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","institution_ids":["https://openalex.org/I100005738"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087430192","display_name":"Brent Nelson","orcid":"https://orcid.org/0000-0002-7523-3269"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brent Nelson","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","institution_ids":["https://openalex.org/I100005738"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018034033","display_name":"Brad Hutchings","orcid":"https://orcid.org/0000-0002-2991-0230"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brad Hutchings","raw_affiliation_strings":["NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NSF Center of High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, USA","institution_ids":["https://openalex.org/I100005738"]},{"raw_affiliation_string":"NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA","institution_ids":["https://openalex.org/I100005738"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I100005738"],"apc_list":null,"apc_paid":null,"fwci":6.4734,"has_fulltext":false,"cited_by_count":48,"citation_normalized_percentile":{"value":0.96864673,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"353","last_page":"356"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7988277077674866},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7350516319274902},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.6706160306930542},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6189923286437988},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6104416847229004},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5805044174194336},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.5728086233139038},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5659810304641724},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5634548664093018},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5616191625595093},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5478805899620056},{"id":"https://openalex.org/keywords/software-prototyping","display_name":"Software prototyping","score":0.4890021085739136},{"id":"https://openalex.org/keywords/computer-aided-design","display_name":"Computer Aided Design","score":0.41298970580101013},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3253704607486725},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32451003789901733},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.2472483217716217},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.21217560768127441},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18461787700653076},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16720497608184814}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7988277077674866},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7350516319274902},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.6706160306930542},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6189923286437988},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6104416847229004},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5805044174194336},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.5728086233139038},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5659810304641724},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5634548664093018},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5616191625595093},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5478805899620056},{"id":"https://openalex.org/C2776697782","wikidata":"https://www.wikidata.org/wiki/Q576460","display_name":"Software prototyping","level":4,"score":0.4890021085739136},{"id":"https://openalex.org/C119823426","wikidata":"https://www.wikidata.org/wiki/Q184793","display_name":"Computer Aided Design","level":2,"score":0.41298970580101013},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3253704607486725},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32451003789901733},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.2472483217716217},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.21217560768127441},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18461787700653076},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16720497608184814},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2010.5681429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2010.5681429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1531732909","https://openalex.org/W1587494897","https://openalex.org/W2008531154","https://openalex.org/W2103127274","https://openalex.org/W2104255322","https://openalex.org/W2105993342","https://openalex.org/W2111608568","https://openalex.org/W6634812723","https://openalex.org/W6676052100"],"related_works":["https://openalex.org/W2030832065","https://openalex.org/W2017340405","https://openalex.org/W3130402546","https://openalex.org/W1562871134","https://openalex.org/W1821888792","https://openalex.org/W119599369","https://openalex.org/W2067167882","https://openalex.org/W2133633735","https://openalex.org/W1577111808","https://openalex.org/W2096445089"],"abstract_inverted_index":{"Designer":[0],"productivity":[1],"for":[2,28,31],"FPGA":[3,14],"design":[4],"is":[5],"significantly":[6],"limited":[7],"by":[8],"the":[9,13,41,52,88],"time-consuming":[10],"nature":[11],"of":[12,45,54,70,76,87],"compilation":[15],"process":[16],"(synthesis,":[17],"map,":[18],"placement,":[19],"and":[20,43,57],"routing).":[21],"However,":[22],"experimentation":[23],"on":[24,85],"alternative":[25],"CAD":[26,62,78],"tools":[27,79],"this":[29,71],"purpose":[30],"Xilinx":[32],"devices":[33],"has":[34],"been":[35],"somewhat":[36],"limited.":[37],"This":[38],"paper":[39,72],"describes":[40],"development":[42],"distribution":[44],"RapidSmith,":[46],"a":[47,60],"software":[48],"library":[49],"to":[50],"facilitate":[51],"manipulation":[53],"XDL":[55],"designs":[56],"upon":[58],"which":[59,80],"complete":[61],"system":[63],"can":[64,81],"be":[65,82],"based.":[66],"The":[67],"demonstration":[68],"portion":[69],"will":[73],"show":[74],"prototypes":[75],"representative":[77],"easily":[83],"built":[84],"top":[86],"RapidSmith":[89],"system.":[90]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":8}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}