{"id":"https://openalex.org/W2107765705","doi":"https://doi.org/10.1109/fpt.2008.4762409","title":"Concurrent timing based and routability driven depopulation technique for FPGA packing","display_name":"Concurrent timing based and routability driven depopulation technique for FPGA packing","publication_year":2008,"publication_date":"2008-12-01","ids":{"openalex":"https://openalex.org/W2107765705","doi":"https://doi.org/10.1109/fpt.2008.4762409","mag":"2107765705"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2008.4762409","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762409","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054424919","display_name":"Audip Pandit","orcid":null},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Audip Pandit","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ","institution_ids":["https://openalex.org/I138006243"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005926278","display_name":"Lakshmi Easwaran","orcid":null},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lakshmi Easwaran","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ","institution_ids":["https://openalex.org/I138006243"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080974820","display_name":"Ali Akoglu","orcid":"https://orcid.org/0000-0001-7982-8991"},"institutions":[{"id":"https://openalex.org/I138006243","display_name":"University of Arizona","ror":"https://ror.org/03m2x1q45","country_code":"US","type":"education","lineage":["https://openalex.org/I138006243"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ali Akoglu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Arizona Tucson, Tucson, AZ, USA","institution_ids":["https://openalex.org/I138006243"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ","institution_ids":["https://openalex.org/I138006243"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5054424919"],"corresponding_institution_ids":["https://openalex.org/I138006243"],"apc_list":null,"apc_paid":null,"fwci":0.3329,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.64751393,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"325","last_page":"328"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7419655323028564},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7304149270057678},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7031461000442505},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.6825796961784363},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6315723061561584},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5924220681190491},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5607220530509949},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5066555142402649},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4628737270832062},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45676305890083313},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4235779345035553},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37674272060394287},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3611244559288025},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13932189345359802},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10719481110572815}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7419655323028564},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7304149270057678},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7031461000442505},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.6825796961784363},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6315723061561584},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5924220681190491},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5607220530509949},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5066555142402649},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4628737270832062},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45676305890083313},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4235779345035553},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37674272060394287},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3611244559288025},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13932189345359802},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10719481110572815},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2008.4762409","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762409","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1591851732","https://openalex.org/W1963908543","https://openalex.org/W2029541370","https://openalex.org/W2095431940","https://openalex.org/W2101356024","https://openalex.org/W2106448546","https://openalex.org/W2113645429","https://openalex.org/W2139637699","https://openalex.org/W2149239312","https://openalex.org/W2150281391","https://openalex.org/W2163599210","https://openalex.org/W3141147179","https://openalex.org/W4241249008","https://openalex.org/W4241806018","https://openalex.org/W6682019771","https://openalex.org/W6792768004"],"related_works":["https://openalex.org/W3011443213","https://openalex.org/W298517545","https://openalex.org/W2111241003","https://openalex.org/W4312291060","https://openalex.org/W4235807419","https://openalex.org/W2144633290","https://openalex.org/W2550704533","https://openalex.org/W2827496155","https://openalex.org/W2890026549","https://openalex.org/W2187775186"],"abstract_inverted_index":{"In":[0,60],"FPGA":[1],"CAD":[2],"flow,":[3],"routability":[4,70],"driven":[5,23],"algorithms":[6,24],"have":[7,25,36],"been":[8,26,37,108],"introduced":[9,27],"to":[10,28,39,122],"improve":[11],"feasibility":[12],"of":[13,34,127,138,153],"mapping":[14],"designs":[15],"onto":[16],"the":[17,77,93,103,111,151],"underlying":[18],"architecture;":[19],"timing":[20,42,72],"and":[21,71,114],"power":[22,44],"meet":[29],"design":[30],"specifications.":[31],"A":[32],"number":[33],"techniques":[35],"proposed":[38],"tackle":[40],"routability,":[41],"or":[43],"objectives":[45],"independently":[46],"during":[47],"clustering":[48,66],"stage.":[49],"However,":[50],"there":[51],"is":[52],"minimal":[53],"work":[54],"that":[55,68],"targets":[56,69],"multiple":[57],"optimization":[58],"goals.":[59],"this":[61],"paper,":[62],"we":[63],"evaluate":[64],"a":[65,82],"technique":[67,89],"goals":[73],"simultaneously.":[74],"We":[75,118],"combine":[76],"timing-driven":[78],"T-VPack":[79],"algorithm":[80],"with":[81,143],"routability-driven":[83],"non-uniform":[84],"depopulation":[85],"scheme":[86],"(T-RDPack).":[87],"Our":[88],"keeps":[90],"clusters":[91,101],"on":[92],"critical":[94,147],"path":[95,148],"fully":[96],"populated,":[97],"while":[98,133],"depopulating":[99],"other":[100],"in":[102,146],"design.":[104],"This":[105],"approach":[106],"has":[107],"implemented":[109],"into":[110],"versatile":[112],"place":[113],"route":[115],"(VPR)":[116],"toolset.":[117],"show":[119],"that,":[120],"compared":[121],"T-VPack,":[123],"channel":[124],"width":[125],"reductions":[126],"11.5%,":[128],"19.1%,":[129],"24.7%":[130],"are":[131],"achieved":[132],"incurring":[134],"an":[135],"area":[136],"overhead":[137],"0.6%,":[139],"3.1%,":[140],"9.1%":[141],"respectively":[142],"negligible":[144],"increase":[145],"delay,":[149],"exceeding":[150],"performance":[152],"T-RPack.":[154]},"counts_by_year":[{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}