{"id":"https://openalex.org/W2166290916","doi":"https://doi.org/10.1109/fpt.2008.4762386","title":"Modelling and compensating for clock skew variability in FPGAs","display_name":"Modelling and compensating for clock skew variability in FPGAs","publication_year":2008,"publication_date":"2008-12-01","ids":{"openalex":"https://openalex.org/W2166290916","doi":"https://doi.org/10.1109/fpt.2008.4762386","mag":"2166290916"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2008.4762386","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762386","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Justin S. Wong","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048050040"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.6659,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.74910352,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"217","last_page":"224"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.8615095615386963},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7808933258056641},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6932509541511536},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6819338798522949},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6201263666152954},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6120010614395142},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.5618016123771667},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5476098656654358},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.5401699542999268},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5390974283218384},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4372161030769348},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3926233649253845},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30717796087265015},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.21438881754875183},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19640561938285828},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09514883160591125},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.06800830364227295}],"concepts":[{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.8615095615386963},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7808933258056641},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6932509541511536},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6819338798522949},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6201263666152954},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6120010614395142},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5618016123771667},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5476098656654358},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.5401699542999268},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5390974283218384},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4372161030769348},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3926233649253845},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30717796087265015},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.21438881754875183},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19640561938285828},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09514883160591125},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.06800830364227295},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C11171543","wikidata":"https://www.wikidata.org/wiki/Q41630","display_name":"Psychoanalysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2008.4762386","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762386","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1490763633","https://openalex.org/W1501346096","https://openalex.org/W1525409241","https://openalex.org/W1973019798","https://openalex.org/W1977505713","https://openalex.org/W1984588379","https://openalex.org/W2016712281","https://openalex.org/W2096746526","https://openalex.org/W2106565868","https://openalex.org/W2114834460","https://openalex.org/W2121437951","https://openalex.org/W2123512677","https://openalex.org/W2127379989","https://openalex.org/W2135097932","https://openalex.org/W2138706204","https://openalex.org/W2141682861","https://openalex.org/W2149864516","https://openalex.org/W2152486274","https://openalex.org/W2178225970","https://openalex.org/W3092521657","https://openalex.org/W3150466398","https://openalex.org/W4238724481","https://openalex.org/W4243059613","https://openalex.org/W4247123921","https://openalex.org/W6631407737","https://openalex.org/W6682236896"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W1596690381","https://openalex.org/W2144282137","https://openalex.org/W2617666058","https://openalex.org/W2127892766","https://openalex.org/W4247089581","https://openalex.org/W2087612346","https://openalex.org/W4233392352"],"abstract_inverted_index":{"As":[0],"integrated":[1],"circuits":[2],"are":[3,30,33,80],"scaled":[4],"down":[5],"it":[6],"becomes":[7],"difficult":[8],"to":[9],"maintain":[10],"uniformity":[11],"in":[12,51,58,61],"process":[13,45],"parameters":[14],"across":[15],"each":[16],"individual":[17],"die.":[18],"To":[19],"avoid":[20],"significant":[21],"performance":[22,37,76],"loss":[23],"through":[24,95],"pessimistic":[25],"over-design":[26],"new":[27],"design":[28],"strategies":[29],"required":[31],"that":[32,85],"cognisant":[34],"of":[35,44,56,72,77,98,114],"within-die":[36],"variability.":[38],"This":[39],"paper":[40],"examines":[41],"the":[42,48,70,75,110,115],"effect":[43],"variability":[46],"on":[47,74,105],"clock":[49,59,63,102],"resources":[50],"FPGA":[52,62,108],"devices.":[53],"A":[54],"model":[55],"variation":[57,87],"skew":[60,86],"networks":[64],"is":[65],"presented.":[66],"Techniques":[67],"for":[68],"reducing":[69],"impact":[71],"variations":[73],"implemented":[78],"designs":[79],"proposed":[81,116],"and":[82,101,112],"analysed,":[83],"demonstrating":[84],"can":[88],"be":[89],"reduced":[90],"by":[91],"70%":[92],"or":[93],"more":[94],"a":[96,106],"combination":[97],"phase":[99],"adjustment":[100],"rerouting.":[103],"Measurements":[104],"Virtex-5":[107],"validate":[109],"feasibility":[111],"benefits":[113],"compensation":[117],"strategies.":[118]},"counts_by_year":[{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
