{"id":"https://openalex.org/W2171546918","doi":"https://doi.org/10.1109/fpt.2008.4762385","title":"Netlist-level IP protection by watermarking for LUT-based FPGAs","display_name":"Netlist-level IP protection by watermarking for LUT-based FPGAs","publication_year":2008,"publication_date":"2008-12-01","ids":{"openalex":"https://openalex.org/W2171546918","doi":"https://doi.org/10.1109/fpt.2008.4762385","mag":"2171546918"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2008.4762385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111887854","display_name":"Moritz Schmid","orcid":null},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Moritz Schmid","raw_affiliation_strings":["Hardware/Software Co-Design, Department of Computer Science, University of Erlangen Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hardware/Software Co-Design, Department of Computer Science, University of Erlangen Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078280066","display_name":"Daniel Ziener","orcid":"https://orcid.org/0000-0001-6449-9208"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Daniel Ziener","raw_affiliation_strings":["Hardware/Software Co-Design, Department of Computer Science, University of Erlangen Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hardware/Software Co-Design, Department of Computer Science, University of Erlangen Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076672029","display_name":"J\u00fcrgen Teich","orcid":"https://orcid.org/0000-0001-6285-5862"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jurgen Teich","raw_affiliation_strings":["Hardware/Software Co-Design, Department of Computer Science, University of Erlangen Nuremberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hardware/Software Co-Design, Department of Computer Science, University of Erlangen Nuremberg, Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111887854"],"corresponding_institution_ids":["https://openalex.org/I181369854"],"apc_list":null,"apc_paid":null,"fwci":1.7262,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":{"value":0.87237419,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"209","last_page":"216"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11241","display_name":"Advanced Malware Detection Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8978676199913025},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8502793312072754},{"id":"https://openalex.org/keywords/watermark","display_name":"Watermark","score":0.7860851287841797},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7855660319328308},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7436480522155762},{"id":"https://openalex.org/keywords/digital-watermarking","display_name":"Digital watermarking","score":0.5449194312095642},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48240387439727783},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4685203731060028},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4379063844680786},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.41223666071891785},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40569016337394714},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3205578923225403},{"id":"https://openalex.org/keywords/embedding","display_name":"Embedding","score":0.24762535095214844},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.112265944480896}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8978676199913025},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8502793312072754},{"id":"https://openalex.org/C164112704","wikidata":"https://www.wikidata.org/wiki/Q7974348","display_name":"Watermark","level":3,"score":0.7860851287841797},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7855660319328308},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7436480522155762},{"id":"https://openalex.org/C150817343","wikidata":"https://www.wikidata.org/wiki/Q875932","display_name":"Digital watermarking","level":3,"score":0.5449194312095642},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48240387439727783},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4685203731060028},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4379063844680786},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.41223666071891785},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40569016337394714},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3205578923225403},{"id":"https://openalex.org/C41608201","wikidata":"https://www.wikidata.org/wiki/Q980509","display_name":"Embedding","level":2,"score":0.24762535095214844},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.112265944480896},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2008.4762385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.161.3876","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.161.3876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www12.informatik.uni-erlangen.de/publications/pub2008/SZT08.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1986199670","https://openalex.org/W1998897310","https://openalex.org/W2003400816","https://openalex.org/W2010021272","https://openalex.org/W2049415734","https://openalex.org/W2057570336","https://openalex.org/W2095001940","https://openalex.org/W2099105559","https://openalex.org/W2116388745","https://openalex.org/W2120440805","https://openalex.org/W2120655216","https://openalex.org/W2134942954","https://openalex.org/W2162517204","https://openalex.org/W2745744674","https://openalex.org/W2911857293","https://openalex.org/W4234400381"],"related_works":["https://openalex.org/W2137394636","https://openalex.org/W2358993821","https://openalex.org/W1516446231","https://openalex.org/W2098152888","https://openalex.org/W1559740347","https://openalex.org/W2040356834","https://openalex.org/W2080353903","https://openalex.org/W2385289568","https://openalex.org/W2381486749","https://openalex.org/W1514507288"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,112,128],"novel":[4],"approach":[5],"to":[6,63,72,89],"watermark":[7,43,79],"FPGA":[8,116],"designs":[9],"on":[10,111],"the":[11,16,21,42,45,56,84,99,102],"netlist":[12],"level.":[13],"We":[14,96],"restrict":[15],"dynamically":[17],"addressable":[18],"part":[19],"of":[20,29,83,86,104,123,131],"logic":[22],"table,":[23],"thus":[24],"freeing":[25],"space":[26],"for":[27],"insertion":[28],"signature":[30],"bits":[31],"into":[32],"lookup":[33],"tables":[34],"(LUTs).":[35],"In":[36],"this":[37,75],"way,":[38],"we":[39,77],"tightly":[40],"integrate":[41],"with":[44],"design":[46],"so":[47],"that":[48],"simply":[49],"removing":[50],"mark":[51],"carrying":[52,80],"components":[53,81],"would":[54],"damage":[55],"intellectual":[57],"property":[58],"core.":[59],"Converting":[60],"functional":[61],"LUTs":[62],"LUT-based":[64],"RAMs":[65],"or":[66],"shift":[67],"registers":[68],"prevents":[69],"deletion":[70],"due":[71],"optimization.":[73],"With":[74],"technique,":[76],"take":[78],"out":[82],"scope":[85],"optimization":[87],"algorithms":[88],"achieve":[90],"complete":[91],"transparency":[92],"towards":[93],"development":[94],"environments.":[95],"can":[97],"extract":[98],"marks":[100],"from":[101],"bitfile":[103],"an":[105],"FPGA.":[106],"The":[107],"method":[108],"was":[109],"tested":[110],"Xilinx":[113],"Virtex-II":[114],"Pro":[115],"and":[117,125],"showed":[118],"low":[119],"overhead":[120],"in":[121],"terms":[122],"timing":[124],"resources":[126],"at":[127],"reasonable":[129],"number":[130],"water-marked":[132],"cells.":[133]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-05T09:01:59.212387","created_date":"2025-10-10T00:00:00"}