{"id":"https://openalex.org/W2154446814","doi":"https://doi.org/10.1109/fpt.2008.4762372","title":"A transition probability based delay measurement method for arbitrary circuits on FPGAs","display_name":"A transition probability based delay measurement method for arbitrary circuits on FPGAs","publication_year":2008,"publication_date":"2008-12-01","ids":{"openalex":"https://openalex.org/W2154446814","doi":"https://doi.org/10.1109/fpt.2008.4762372","mag":"2154446814"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2008.4762372","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762372","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Justin S. J. Wong","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5051758515"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":2.0797,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.88812714,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"105","last_page":"112"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8316137790679932},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7763597965240479},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.7077993154525757},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6751081347465515},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.633954644203186},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5374408960342407},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5083369612693787},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.45789724588394165},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4169619381427765},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3984350264072418},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3953135907649994},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38447195291519165},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.37838664650917053},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14441704750061035},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10913145542144775}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8316137790679932},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7763597965240479},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7077993154525757},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6751081347465515},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.633954644203186},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5374408960342407},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5083369612693787},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.45789724588394165},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4169619381427765},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3984350264072418},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3953135907649994},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38447195291519165},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.37838664650917053},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14441704750061035},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10913145542144775},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2008.4762372","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762372","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1510355813","https://openalex.org/W1532888190","https://openalex.org/W2016712281","https://openalex.org/W2020640915","https://openalex.org/W2055179355","https://openalex.org/W2096227207","https://openalex.org/W2102755988","https://openalex.org/W2141682861","https://openalex.org/W2144773387","https://openalex.org/W2155042027","https://openalex.org/W2170735577","https://openalex.org/W2532498749","https://openalex.org/W3141297747","https://openalex.org/W4254201402"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W4393353016","https://openalex.org/W2067456700","https://openalex.org/W2013484291"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,52,86,98],"novel":[4],"test":[5,55],"method":[6,35,62,106],"for":[7],"measuring":[8],"the":[9,28,42,47],"worst":[10],"case":[11],"path":[12],"delay":[13],"of":[14,27,54,68],"any":[15],"circuit":[16],"on":[17,38,46,72],"an":[18,73,78,82],"FPGA,":[19],"combinatorial":[20],"or":[21],"sequential,":[22],"where":[23],"little":[24],"prior":[25],"knowledge":[26],"circuitpsilas":[29,48],"internal":[30],"structure":[31],"is":[32,36,58,63],"required.":[33],"The":[34,61,89],"based":[37],"detecting":[39],"changes":[40],"in":[41],"transition":[43],"probability":[44],"profile":[45],"output":[49],"nodes":[50],"while":[51],"range":[53],"clock":[56],"frequencies":[57],"stepped":[59],"through.":[60],"applied":[64],"to":[65,94,111],"three":[66],"classes":[67],"circuits,":[69],"all":[70],"implemented":[71],"Altera":[74],"Cyclone":[75],"III":[76],"FPGA:":[77],"adder":[79],"carry":[80],"chain,":[81],"embedded":[83],"multiplier":[84],"and":[85,107],"linear-feedback":[87],"shift-register.":[88],"measured":[90],"delays":[91],"are":[92],"compared":[93],"that":[95],"found":[96],"by":[97],"previously":[99],"published,":[100],"but":[101],"much":[102],"more":[103],"time":[104],"consuming,":[105],"their":[108],"results":[109],"match":[110],"within":[112],"12%.":[113]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}