{"id":"https://openalex.org/W2039505506","doi":"https://doi.org/10.1109/fpt.2008.4762357","title":"FPGA timing, power, signal integrity and other challenges at 65 and 45 nm","display_name":"FPGA timing, power, signal integrity and other challenges at 65 and 45 nm","publication_year":2008,"publication_date":"2008-12-01","ids":{"openalex":"https://openalex.org/W2039505506","doi":"https://doi.org/10.1109/fpt.2008.4762357","mag":"2039505506"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2008.4762357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762357","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036033566","display_name":"Paul Leventis","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Paul Leventis","raw_affiliation_strings":["Altera Vietnam Technology Center, Vietnam","Altera Vietnam Technol. Center"],"affiliations":[{"raw_affiliation_string":"Altera Vietnam Technology Center, Vietnam","institution_ids":[]},{"raw_affiliation_string":"Altera Vietnam Technol. Center","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5036033566"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09077996,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"lxvi","last_page":"lxvi"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7712659239768982},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7268796563148499},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7005370259284973},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6546463966369629},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.6262902617454529},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5766502618789673},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5303842425346375},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.4743947982788086},{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.47146087884902954},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4429682791233063},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4383425712585449},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4103717803955078},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39230453968048096},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3635869026184082},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21335765719413757},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1355484426021576},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09338068962097168},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09294122457504272},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.08493354916572571}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7712659239768982},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7268796563148499},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7005370259284973},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6546463966369629},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.6262902617454529},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5766502618789673},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5303842425346375},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.4743947982788086},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.47146087884902954},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4429682791233063},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4383425712585449},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4103717803955078},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39230453968048096},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3635869026184082},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21335765719413757},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1355484426021576},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09338068962097168},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09294122457504272},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.08493354916572571},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2008.4762357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2008.4762357","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/12","display_name":"Responsible consumption and production","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2965410099","https://openalex.org/W4235454973","https://openalex.org/W4386105410","https://openalex.org/W2148913576","https://openalex.org/W3097351224","https://openalex.org/W2250058922","https://openalex.org/W2533759086","https://openalex.org/W2246813539","https://openalex.org/W2097451288","https://openalex.org/W2394154616"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"The":[4],"steady":[5],"march":[6],"towards":[7],"smaller":[8],"feature":[9],"sizes":[10],"has":[11,74],"made":[12],"ASIC":[13],"design,":[14,47],"modeling":[15,87,95],"and":[16,44,70,76,80,88,96,100,110],"verification":[17],"increasingly":[18],"more":[19],"challenging.":[20],"FPGAs":[21],"present":[22,59],"an":[23],"even":[24],"greater":[25],"challenge,":[26],"since":[27],"this":[28,55],"analysis":[29,69],"work":[30],"must":[31],"be":[32],"performed":[33],"on":[34,78,86],"the":[35,39,52,67],"user":[36],"desktop,":[37],"at":[38],"push":[40],"of":[41,63,66],"a":[42,60,64],"button":[43],"for":[45],"any":[46],"without":[48],"over-burdening":[49],"users":[50],"with":[51],"details.":[53],"In":[54],"talk,":[56],"I":[57,83],"will":[58,84],"brief":[61],"overview":[62],"few":[65],"modeling,":[68],"optimization":[71,90],"challenges":[72],"Altera":[73],"faced":[75],"overcome":[77],"65nm":[79],"45nm":[81],"devices.":[82],"touch":[85],"simultaneous":[89,111],"across":[91],"timing":[92],"corners,":[93],"hold-time":[94],"optimization,":[97],"on-die":[98],"variation":[99],"jitter,":[101],"end-of-life":[102],"effects,":[103],"metastability":[104],"analysis,":[105],"advanced":[106],"power":[107],"management":[108],"techniques,":[109],"switching":[112],"noise.":[113]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}