{"id":"https://openalex.org/W2069803096","doi":"https://doi.org/10.1109/fpt.2007.4439286","title":"A Programmable Load/Store Unit on C-based Hardware Design for FPGA","display_name":"A Programmable Load/Store Unit on C-based Hardware Design for FPGA","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2069803096","doi":"https://doi.org/10.1109/fpt.2007.4439286","mag":"2069803096"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2007.4439286","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439286","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075659609","display_name":"Akira Yamawaki","orcid":"https://orcid.org/0000-0002-8723-0620"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akira Yamawaki","raw_affiliation_strings":["Department of Erectronic Engineering, Kyushu Institute of Technology, Kitakyushu, Japan","Kyushu Institute of Technology, Kitakyushu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Erectronic Engineering, Kyushu Institute of Technology, Kitakyushu, Japan","institution_ids":["https://openalex.org/I207014233"]},{"raw_affiliation_string":"Kyushu Institute of Technology, Kitakyushu","institution_ids":["https://openalex.org/I207014233"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071214096","display_name":"Masahiko Iwane","orcid":null},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiko Iwane","raw_affiliation_strings":["Department of Erectronic Engineering, Kyushu Institute of Technology, Kitakyushu, Japan","Kyushu Institute of Technology, Kitakyushu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Erectronic Engineering, Kyushu Institute of Technology, Kitakyushu, Japan","institution_ids":["https://openalex.org/I207014233"]},{"raw_affiliation_string":"Kyushu Institute of Technology, Kitakyushu","institution_ids":["https://openalex.org/I207014233"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10117625,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"j88?d i","issue":null,"first_page":"361","last_page":"364"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7919120788574219},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7855626344680786},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6874089241027832},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6108835935592651},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5266204476356506},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5130020976066589},{"id":"https://openalex.org/keywords/direct-memory-access","display_name":"Direct memory access","score":0.46044620871543884},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33910226821899414},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3245340585708618}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7919120788574219},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7855626344680786},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6874089241027832},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6108835935592651},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5266204476356506},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5130020976066589},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.46044620871543884},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33910226821899414},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3245340585708618},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2776175482","wikidata":"https://www.wikidata.org/wiki/Q1195816","display_name":"Transfer (computing)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2007.4439286","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439286","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2104683808","https://openalex.org/W2129150326","https://openalex.org/W2145853384","https://openalex.org/W2145947338"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"to":[3,10],"introduce":[4],"a":[5,35,95],"programmable":[6],"load/store":[7],"unit":[8],"(LSU)":[9],"C-based":[11],"hardware":[12,31,40,89],"design":[13],"for":[14,30],"an":[15,104],"FPGA.":[16],"The":[17,39,61,69],"LSU":[18,44,62,74,93],"provides":[19],"flexible":[20],"memory":[21,27,84],"access":[22,28,85],"methods":[23],"that":[24,72],"can":[25,45,75],"hide":[26],"latency":[29],"modules":[32,90],"generated":[33],"by":[34],"high-level":[36],"synthesis":[37],"tool.":[38],"module":[41],"with":[42,91,103],"the":[43,73,78,82,88,92],"treat":[46],"efficiently":[47],"not":[48],"only":[49],"simple":[50],"streaming":[51],"accesses":[52,56],"but":[53],"also":[54],"sophisticated":[55],"such":[57],"as":[58],"image":[59],"processing.":[60],"is":[63],"evaluated":[64],"using":[65],"two":[66],"case":[67],"studies.":[68],"result":[70],"shows":[71],"significantly":[76],"reduce":[77],"burden":[79],"of":[80,97],"designing":[81],"dedicated":[83],"circuits":[86],"and":[87,99],"achieve":[94],"speedup":[96],"16.5":[98],"27.3":[100],"times":[101],"compared":[102],"embedded":[105],"processor.":[106]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}