{"id":"https://openalex.org/W2155173652","doi":"https://doi.org/10.1109/fpt.2007.4439266","title":"NICFlex: A Functional Verification Accelerator for An RTL NIC Design","display_name":"NICFlex: A Functional Verification Accelerator for An RTL NIC Design","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2155173652","doi":"https://doi.org/10.1109/fpt.2007.4439266","mag":"2155173652"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2007.4439266","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101655022","display_name":"Xianyang Jiang","orcid":"https://orcid.org/0000-0001-6953-229X"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xianyang Jiang","raw_affiliation_strings":["Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, China","institution_ids":["https://openalex.org/I4210090176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042058386","display_name":"Xiaomin Li","orcid":"https://orcid.org/0000-0001-7587-0543"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaomin Li","raw_affiliation_strings":["Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy and Sciences, China","institution_ids":["https://openalex.org/I4210090176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054793931","display_name":"Yue Tian","orcid":"https://orcid.org/0000-0002-4102-0900"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yue Tian","raw_affiliation_strings":["Chinese Academy of Sciences, China"],"affiliations":[{"raw_affiliation_string":"Chinese Academy of Sciences, China","institution_ids":["https://openalex.org/I19820366"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100437036","display_name":"Kai Wang","orcid":"https://orcid.org/0000-0002-6170-4744"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kai Wang","raw_affiliation_strings":["Chinese Academy of Sciences, China"],"affiliations":[{"raw_affiliation_string":"Chinese Academy of Sciences, China","institution_ids":["https://openalex.org/I19820366"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101655022"],"corresponding_institution_ids":["https://openalex.org/I4210090176"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14534248,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"281","last_page":"284"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.8616984486579895},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7619825601577759},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.7123216986656189},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.6940548419952393},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5984950661659241},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5798486471176147},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.503523051738739},{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.500758171081543},{"id":"https://openalex.org/keywords/software-verification","display_name":"Software verification","score":0.4960571229457855},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.45971229672431946},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.39113134145736694},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3694261610507965},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3450324535369873},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23242345452308655},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.16085034608840942},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.13981586694717407},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1182829737663269},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.09838494658470154}],"concepts":[{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.8616984486579895},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7619825601577759},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.7123216986656189},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.6940548419952393},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5984950661659241},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5798486471176147},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.503523051738739},{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.500758171081543},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.4960571229457855},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.45971229672431946},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.39113134145736694},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3694261610507965},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3450324535369873},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23242345452308655},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.16085034608840942},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.13981586694717407},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1182829737663269},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.09838494658470154}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2007.4439266","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439266","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W72701029","https://openalex.org/W179132751","https://openalex.org/W1525126243","https://openalex.org/W1597778685","https://openalex.org/W1987749257","https://openalex.org/W2089258895","https://openalex.org/W2097054561","https://openalex.org/W2102061396","https://openalex.org/W2131793732","https://openalex.org/W2145711916","https://openalex.org/W2155388085","https://openalex.org/W2163022561","https://openalex.org/W2184286011","https://openalex.org/W4244500912","https://openalex.org/W4251681643","https://openalex.org/W6603043066","https://openalex.org/W6607377921","https://openalex.org/W6635867622","https://openalex.org/W6673073180","https://openalex.org/W6675424803","https://openalex.org/W6681476949","https://openalex.org/W6686209966"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2929969821","https://openalex.org/W3120172095","https://openalex.org/W2363848262","https://openalex.org/W2392047570","https://openalex.org/W4205300843","https://openalex.org/W4214538333","https://openalex.org/W3155012083","https://openalex.org/W2035244079","https://openalex.org/W2890757532"],"abstract_inverted_index":{"A":[0],"short":[1],"time-to-market":[2],"is":[3,24,60,95,138],"very":[4],"important":[5],"for":[6,28,39,62,129,140],"a":[7,25,29,41,45,55,63,76,80,88,106,111,146],"chip,":[8],"and":[9,31,79,91],"verification":[10,37,57,72,114,123,143],"takes":[11],"the":[12,92,121],"most":[13],"(about":[14],"70%)":[15],"of":[16,124,131,145],"its":[17],"design":[18,128],"time.":[19],"Network":[20],"interface":[21],"controller":[22],"(NIC)":[23],"key":[26],"component":[27],"supercomputer":[30],"other":[32],"computing":[33],"systems.":[34],"To":[35],"reduce":[36],"time":[38],"such":[40],"market-demanding":[42],"product":[43],"plays":[44],"great":[46],"role":[47],"in":[48],"relevant":[49],"system":[50],"design.":[51,69,149],"In":[52],"this":[53],"paper,":[54],"functional":[56,122,142],"accelerator":[58],"NICFlex":[59,70,118,137],"presented":[61],"register":[64],"transfer":[65],"level":[66],"(RTL)":[67],"NIC":[68,107,127],"accelerates":[71],"process":[73],"by":[74],"both":[75],"software":[77,84],"part":[78,85,94],"hardware":[81,93],"part.":[82],"The":[83],"runs":[86],"as":[87],"simulation":[89,113],"thread,":[90],"mapped":[96],"into":[97],"field":[98],"programmable":[99],"gate":[100],"array":[101],"(FPGA)":[102],"logic":[103],"together":[104],"with":[105],"wrapper.":[108],"Compared":[109],"to":[110],"conventional":[112],"method":[115],"using":[116],"ModelSim,":[117],"can":[119],"accelerate":[120],"an":[125],"RTL":[126,148],"hundreds":[130],"times":[132],"or":[133],"more.":[134],"With":[135],"extension,":[136],"promising":[139],"any":[141],"acceleration":[144],"generic":[147]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}