{"id":"https://openalex.org/W2039282783","doi":"https://doi.org/10.1109/fpt.2007.4439255","title":"Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow Architectures","display_name":"Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow Architectures","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2039282783","doi":"https://doi.org/10.1109/fpt.2007.4439255","mag":"2039282783"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2007.4439255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439255","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048653669","display_name":"Kai\u2010Jung Shih","orcid":"https://orcid.org/0000-0002-3395-8341"},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Kai-Jung Shih","raw_affiliation_strings":["Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan","Nat. Chung-Cheng Univ., ChiaYi"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Nat. Chung-Cheng Univ., ChiaYi","institution_ids":["https://openalex.org/I148099254"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017804351","display_name":"Chin-Chieh Hung","orcid":null},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chin-Chieh Hung","raw_affiliation_strings":["Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan","Nat. Chung-Cheng Univ., ChiaYi"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Nat. Chung-Cheng Univ., ChiaYi","institution_ids":["https://openalex.org/I148099254"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050423310","display_name":"Pao\u2010Ann Hsiung","orcid":"https://orcid.org/0000-0002-3639-1467"},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Pao-Ann Hsiung","raw_affiliation_strings":["Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan","Nat. Chung-Cheng Univ., ChiaYi"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Nat. Chung-Cheng Univ., ChiaYi","institution_ids":["https://openalex.org/I148099254"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048653669"],"corresponding_institution_ids":["https://openalex.org/I148099254"],"apc_list":null,"apc_paid":null,"fwci":0.9548,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.76595541,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"237","last_page":"240"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8068697452545166},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.7072919607162476},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.6008005738258362},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6002373099327087},{"id":"https://openalex.org/keywords/space-based-architecture","display_name":"Space-based architecture","score":0.4991605281829834},{"id":"https://openalex.org/keywords/data-architecture","display_name":"Data architecture","score":0.48277488350868225},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48249053955078125},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47487160563468933},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"Dataflow architecture","score":0.42085039615631104},{"id":"https://openalex.org/keywords/reference-architecture","display_name":"Reference architecture","score":0.395632803440094},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3943175673484802},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19602027535438538},{"id":"https://openalex.org/keywords/software-architecture","display_name":"Software architecture","score":0.14116549491882324},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09342926740646362},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.08955538272857666}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8068697452545166},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.7072919607162476},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.6008005738258362},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6002373099327087},{"id":"https://openalex.org/C55627697","wikidata":"https://www.wikidata.org/wiki/Q7572175","display_name":"Space-based architecture","level":5,"score":0.4991605281829834},{"id":"https://openalex.org/C94070970","wikidata":"https://www.wikidata.org/wiki/Q638422","display_name":"Data architecture","level":5,"score":0.48277488350868225},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48249053955078125},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47487160563468933},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.42085039615631104},{"id":"https://openalex.org/C55356503","wikidata":"https://www.wikidata.org/wiki/Q2136675","display_name":"Reference architecture","level":4,"score":0.395632803440094},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3943175673484802},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19602027535438538},{"id":"https://openalex.org/C35869016","wikidata":"https://www.wikidata.org/wiki/Q846636","display_name":"Software architecture","level":3,"score":0.14116549491882324},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09342926740646362},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.08955538272857666},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2007.4439255","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439255","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.159.1641","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.159.1641","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.ccu.edu.tw/~pahsiung/publications/papers/MSA_ICFPT2007.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1492380776","https://openalex.org/W1830620847","https://openalex.org/W1992393251","https://openalex.org/W2022573326","https://openalex.org/W2099971283","https://openalex.org/W2163764012","https://openalex.org/W2167672866","https://openalex.org/W2917583897","https://openalex.org/W6684293632"],"related_works":["https://openalex.org/W2356280685","https://openalex.org/W4238407057","https://openalex.org/W1152672851","https://openalex.org/W2905071167","https://openalex.org/W2342672932","https://openalex.org/W4289655526","https://openalex.org/W2611496792","https://openalex.org/W4226237158","https://openalex.org/W2364344445","https://openalex.org/W227155913"],"abstract_inverted_index":{"Dynamically":[0],"reconfigurable":[1],"systems":[2],"either":[3],"adopt":[4],"a":[5,10,46,55,99],"processor-controlled":[6],"networked":[7,17,113],"architecture":[8,88,108,114,126],"or":[9],"sequencer-controlled":[11],"data":[12,24,30,43,73,124],"flow":[13,31,125],"architecture.":[14,85],"In":[15],"the":[16,19,29,33,39,42,64,67,71,82,87,106,112,123],"architecture,":[18,32,59],"processor":[20,40,65],"is":[21,35,77,89,109],"overloaded":[22],"with":[23,81],"transfer":[25],"requests,":[26],"whereas":[27],"in":[28,115,127],"burden":[34],"completely":[36],"shifted":[37],"from":[38],"to":[41,69,97,111,122],"sequencer.":[44],"As":[45],"tradeoff":[47],"between":[48],"these":[49],"two":[50],"extremes,":[51],"this":[52],"work":[53],"proposes":[54],"novel":[56],"module":[57],"sequencer":[58,68],"which":[60],"not":[61],"only":[62],"allows":[63],"and":[66,121],"share":[70],"heavy":[72],"communication":[74,119],"load,":[75],"but":[76],"also":[78],"more":[79],"coherent":[80],"conventional":[83],"processor-FPGA":[84],"Further,":[86],"highly":[90],"flexible":[91],"because":[92],"it":[93],"can":[94],"be":[95],"tuned":[96],"fit":[98],"particular":[100],"application.":[101],"Application":[102],"examples":[103],"show":[104],"how":[105],"proposed":[107],"superior":[110],"terms":[116,128],"of":[117,129],"lower":[118],"load":[120],"reduced":[130],"system":[131],"complexity.":[132]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
