{"id":"https://openalex.org/W2016712281","doi":"https://doi.org/10.1109/fpt.2007.4439227","title":"Self-characterization of Combinatorial Circuit Delays in FPGAs","display_name":"Self-characterization of Combinatorial Circuit Delays in FPGAs","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2016712281","doi":"https://doi.org/10.1109/fpt.2007.4439227","mag":"2016712281"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2007.4439227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051758515","display_name":"Justin S. J. Wong","orcid":"https://orcid.org/0000-0002-4378-1199"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Justin S. J. Wong","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK","Imperial College London,#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London,#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048050040","display_name":"Pete Sedcole","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pete Sedcole","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK","Department of Electrical & Electronic Engineering, Imperial College London, South Kensington campus, London SW7 2AZ, UK. pete.sedcole@imperial.ac.uk"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, South Kensington campus, London SW7 2AZ, UK. pete.sedcole@imperial.ac.uk","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Imperial College London, London, UK","Department of Electrical & Electronic Engineering, Imperial College London, South Kensington campus, London SW7 2AZ, UK. p.cheung@imperial.ac.uk"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Imperial College London, South Kensington campus, London SW7 2AZ, UK. p.cheung@imperial.ac.uk","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5051758515"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":3.812,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.92975917,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"17","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8900799751281738},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.720359206199646},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5160512328147888},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.49356257915496826},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4494655728340149},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43721306324005127},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4348784387111664},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4318106770515442},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42709192633628845},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.4185497760772705},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41340500116348267},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36020636558532715},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10472559928894043}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8900799751281738},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.720359206199646},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5160512328147888},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.49356257915496826},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4494655728340149},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43721306324005127},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4348784387111664},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4318106770515442},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42709192633628845},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.4185497760772705},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41340500116348267},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36020636558532715},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10472559928894043},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2007.4439227","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2007.4439227","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Conference on Field-Programmable Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W306641292","https://openalex.org/W1532888190","https://openalex.org/W2055179355","https://openalex.org/W2096227207","https://openalex.org/W2102755988","https://openalex.org/W2121955149","https://openalex.org/W2126008551","https://openalex.org/W2141682861","https://openalex.org/W2144773387","https://openalex.org/W2155042027","https://openalex.org/W2170735577","https://openalex.org/W2532498749","https://openalex.org/W4254201402","https://openalex.org/W6681343092"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2373535795","https://openalex.org/W2082487009","https://openalex.org/W2406926880","https://openalex.org/W4237139544","https://openalex.org/W2787763930"],"abstract_inverted_index":{"This":[0,119],"paper":[1],"proposes":[2],"a":[3,35,61,134],"built-in":[4],"self-test":[5],"(BIST)":[6],"method":[7,74,91,121],"to":[8,32,94,115,131],"measure":[9],"accurately":[10],"the":[11,21,43,51,73,78,82,117,123,138],"combinatorial":[12,44,55],"circuit":[13,45,56],"delays":[14],"on":[15,84],"an":[16,85,95],"FPGA.":[17],"The":[18,90],"flexibility":[19],"of":[20,37,53,64,72,77,80,112,136,140],"on-chip":[22],"clock":[23],"generation":[24],"capability":[25],"found":[26],"in":[27,42,105,129],"modern":[28],"FPGAs":[29,132],"is":[30,46,87],"employed":[31],"step":[33],"through":[34],"range":[36],"frequencies":[38],"until":[39],"timing":[40,62,127],"failure":[41],"detected.":[47],"In":[48],"this":[49],"way,":[50],"delay":[52,79],"any":[54],"can":[57],"be":[58],"determined":[59],"with":[60],"resolution":[63],"1":[65],"ps":[66],"or":[67],"lower.":[68],"A":[69,100],"parallel":[70],"implementation":[71],"for":[75,125],"self-characterization":[76,102,120],"all":[81],"LUTs":[83],"FPGA":[86,98],"also":[88],"proposed.":[89],"was":[92,103],"applied":[93],"Altera":[96],"Cyclone-II":[97],"(EP2C35).":[99],"complete":[101],"achieved":[104],"3":[106],"seconds,":[107],"utilizing":[108],"only":[109],"13":[110],"kbit":[111],"block":[113],"RAM":[114],"store":[116],"results.":[118],"paves":[122],"way":[124],"matching":[126],"requirements":[128],"designs":[130],"as":[133],"means":[135],"combating":[137],"problem":[139],"process":[141],"variations.":[142]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}