{"id":"https://openalex.org/W2119694072","doi":"https://doi.org/10.1109/fpt.2004.1393262","title":"Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks","display_name":"Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W2119694072","doi":"https://doi.org/10.1109/fpt.2004.1393262","mag":"2119694072"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2004.1393262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2004.1393262","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023455335","display_name":"Nastaran Baradaran","orcid":null},"institutions":[{"id":"https://openalex.org/I2801204180","display_name":"Marina Del Rey Hospital","ror":"https://ror.org/05wqyfz02","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I2801204180"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"N. Baradaran","raw_affiliation_strings":["Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","Information Sci. Inst., Southern California Univ., Marina del Rey, CA, USA"],"affiliations":[{"raw_affiliation_string":"Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","institution_ids":["https://openalex.org/I2801204180"]},{"raw_affiliation_string":"Information Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103206432","display_name":"Joon-Seok Park","orcid":"https://orcid.org/0009-0001-9427-6571"},"institutions":[{"id":"https://openalex.org/I2801204180","display_name":"Marina Del Rey Hospital","ror":"https://ror.org/05wqyfz02","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I2801204180"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joonseok Park","raw_affiliation_strings":["Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","Information Sci. Inst., Southern California Univ., Marina del Rey, CA, USA"],"affiliations":[{"raw_affiliation_string":"Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","institution_ids":["https://openalex.org/I2801204180"]},{"raw_affiliation_string":"Information Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042540194","display_name":"Pedro C. Diniz","orcid":"https://orcid.org/0000-0003-3131-9367"},"institutions":[{"id":"https://openalex.org/I2801204180","display_name":"Marina Del Rey Hospital","ror":"https://ror.org/05wqyfz02","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I2801204180"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P.C. Diniz","raw_affiliation_strings":["Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","Information Sci. Inst., Southern California Univ., Marina del Rey, CA, USA"],"affiliations":[{"raw_affiliation_string":"Inf. Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","institution_ids":["https://openalex.org/I2801204180"]},{"raw_affiliation_string":"Information Sci. Inst., Southern California Univ., Marina del Rey, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5023455335"],"corresponding_institution_ids":["https://openalex.org/I2801204180"],"apc_list":null,"apc_paid":null,"fwci":2.1064,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.86728435,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"145","last_page":"152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8546497821807861},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7104696035385132},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7066943645477295},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6756383776664734},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.559984564781189},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5439758896827698},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5001986026763916},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4712260961532593},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4695606529712677},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4458862543106079},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.4269885718822479},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38099777698516846},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3399515151977539},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25350314378738403},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.08033031225204468}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8546497821807861},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7104696035385132},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7066943645477295},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6756383776664734},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.559984564781189},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5439758896827698},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5001986026763916},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4712260961532593},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4695606529712677},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4458862543106079},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.4269885718822479},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38099777698516846},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3399515151977539},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25350314378738403},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.08033031225204468},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2004.1393262","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2004.1393262","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1554668868","https://openalex.org/W1966708457","https://openalex.org/W2029779044","https://openalex.org/W2108315152","https://openalex.org/W2123183104","https://openalex.org/W2135906862","https://openalex.org/W2137300667","https://openalex.org/W2152506070","https://openalex.org/W2157828735","https://openalex.org/W2162203206","https://openalex.org/W4237977381","https://openalex.org/W4250047106","https://openalex.org/W6633243300"],"related_works":["https://openalex.org/W2371266106","https://openalex.org/W2117382851","https://openalex.org/W2382449560","https://openalex.org/W2767298477","https://openalex.org/W2110432562","https://openalex.org/W2025344","https://openalex.org/W2117864619","https://openalex.org/W2090337950","https://openalex.org/W2104121286","https://openalex.org/W2152155870"],"abstract_inverted_index":{"Contemporary":[0],"configurable":[1,120],"architectures":[2],"have":[3],"dedicated":[4],"internal":[5,80],"functional":[6],"units":[7],"such":[8],"as":[9],"multipliers,":[10],"high-capacity":[11],"storage":[12],"RAM,":[13],"and":[14,83,131],"even":[15,135],"CAM":[16],"blocks.":[17],"These":[18],"RAM":[19,51,81,112],"blocks":[20,52,82],"allow":[21],"the":[22,31,36,50,54,79,105],"implementations":[23],"to":[24,27],"cache":[25],"data":[26,45,69,74,110],"be":[28,76],"reused":[29],"in":[30,53,78,111,132],"near":[32],"future,":[33],"thereby":[34],"avoiding":[35],"latency":[37,107],"of":[38,56,60,91,108],"external":[39],"memory":[40],"accesses.":[41],"We":[42],"present":[43],"a":[44,57,67,89,96],"allocation":[46],"algorithm":[47],"that":[48,103,115,124],"utilizes":[49],"presence":[55],"limited":[58],"number":[59],"hardware":[61],"registers.":[62],"This":[63],"algorithm,":[64],"based":[65],"on":[66],"compiler":[68],"reuse":[70],"analysis,":[71],"determines":[72],"which":[73],"should":[75],"cached":[77],"when.":[84],"The":[85],"preliminary":[86],"results,":[87],"for":[88],"set":[90],"image/signal":[92],"processing":[93],"kernels":[94],"targeting":[95],"Xilinx":[97],"Virtex/spl":[98],"trade/":[99],"FPGA":[100],"device,":[101],"reveal":[102],"despite":[104],"increase":[106],"accessing":[109],"blocks,":[113],"designs":[114,123],"use":[116,126],"them":[117],"require":[118],"smaller":[119],"resources":[121],"than":[122],"exclusively":[125],"registers,":[127],"while":[128],"attaining":[129],"comparable":[130],"some":[133],"cases":[134],"better":[136],"performance.":[137]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}