{"id":"https://openalex.org/W1516473290","doi":"https://doi.org/10.1109/fpt.2003.1275788","title":"Combined run-time area allocation and long line re-routing for reconfigurable computing","display_name":"Combined run-time area allocation and long line re-routing for reconfigurable computing","publication_year":2004,"publication_date":"2004-05-13","ids":{"openalex":"https://openalex.org/W1516473290","doi":"https://doi.org/10.1109/fpt.2003.1275788","mag":"1516473290"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2003.1275788","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2003.1275788","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047175454","display_name":"Mark Jasiunas","orcid":null},"institutions":[{"id":"https://openalex.org/I170239107","display_name":"University of South Australia","ror":"https://ror.org/01p93h210","country_code":"AU","type":"education","lineage":["https://openalex.org/I170239107"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"M.D. Jasiunas","raw_affiliation_strings":["Reconfigurable Computing Laboratory, Advanced Computing Research Centre, University of South Australia, Mawson Lakes, SA, Australia","Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Laboratory, Advanced Computing Research Centre, University of South Australia, Mawson Lakes, SA, Australia","institution_ids":["https://openalex.org/I170239107"]},{"raw_affiliation_string":"Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia","institution_ids":["https://openalex.org/I170239107"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5047175454"],"corresponding_institution_ids":["https://openalex.org/I170239107"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"407","last_page":"410"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8095715045928955},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7118058800697327},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6316803693771362},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6186168789863586},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.4932636618614197},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4690708816051483},{"id":"https://openalex.org/keywords/queueing-theory","display_name":"Queueing theory","score":0.4421970546245575},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.43158233165740967},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43004870414733887},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4137907922267914},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3521963357925415},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2579859495162964}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8095715045928955},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7118058800697327},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6316803693771362},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6186168789863586},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.4932636618614197},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4690708816051483},{"id":"https://openalex.org/C22684755","wikidata":"https://www.wikidata.org/wiki/Q847526","display_name":"Queueing theory","level":2,"score":0.4421970546245575},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.43158233165740967},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43004870414733887},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4137907922267914},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3521963357925415},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2579859495162964},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2003.1275788","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2003.1275788","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"On-line":[0],"(run":[1],"time)":[2],"algorithms":[3],"for":[4,38,75,143,264],"allocation":[5,60,89,116,258],"of":[6,30,57,111,124,135,167,171,190,194,210,232,267],"area":[7,59,136,192,222,248,255],"and":[8,90,137],"routing":[9,70,91,235],"resources":[10,125,193],"are":[11,19,34,78,92,140,162],"a":[12,104],"requirement":[13],"if":[14],"field":[15],"programmable":[16],"logic":[17],"applications":[18,40,76,130,223,227],"to":[20,23,107,158,181,186,201,205,229,239,275],"be":[21,199],"loaded":[22],"the":[24,27,35,55,64,109,146,191,195,230,240,253,265],"FPGA":[25,174,254],"at":[26,94],"arbitrary":[28],"request":[29],"users.":[31],"Long":[32],"lines":[33],"preferred":[36],"interconnect":[37],"such":[39],"on":[41,63,72,117,145,164],"dense":[42],"FPGAs":[43],"as":[44],"they":[45],"provide":[46],"low":[47],"delay":[48],"channels.":[49],"In":[50],"this":[51,152,172,273],"paper":[52,101,274],"we":[53],"investigate":[54],"combination":[56],"an":[58,127,214],"algorithm":[61],"based":[62,71,163],"Minkowski":[65],"sum":[66],"with":[67,279],"run":[68,95,113,182],"time":[69,96,114,139,183,209],"line":[73,234],"probing":[74],"that":[77,88,151,256],"linked":[79],"only":[80],"by":[81,86],"long":[82,233],"lines.":[83],"We":[84],"show":[85],"construction":[87],"feasible":[93],"using":[97],"these":[98,211],"algorithms.":[99],"The":[100,119,207],"then":[102],"introduces":[103],"new":[105,120,178,262],"metric":[106,121,153],"measure":[108],"performance":[110],"dynamic":[112,173],"resource":[115],"FPGAs.":[118],"measures":[122,160],"fragmentation":[123],"in":[126,272],"environment":[128,175],"where":[129,246],"selected":[131],"from":[132],"statistical":[133],"distributions":[134],"execution":[138],"continuously":[141],"queued":[142],"placement":[144],"FPGA.":[147],"It":[148],"is":[149,154,213,259,270],"argued":[150],"more":[155],"realistic":[156],"compared":[157],"other":[159,226,241],"which":[161],"static":[165],"model":[166],"allocation.":[168],"A":[169,261],"simulation":[170],"has":[176],"revealed":[177],"behaviours":[179],"related":[180],"reconfiguration.":[184],"Firstly,":[185],"maintain":[187],"full":[188],"utilisation":[189],"FPGA,":[196],"it":[197],"will":[198],"necessary":[200],"queue":[202],"tasks":[203,212],"prior":[204],"execution.":[206],"queuing":[208],"added":[215],"overhead":[216],"not":[217],"previously":[218],"reported.":[219],"Secondly,":[220],"small":[221,268],"may":[224,250],"block":[225],"due":[228],"exhaustion":[231],"resources.":[236],"This":[237],"adds":[238],"already":[242],"observed":[243],"blocking":[244,277],"behaviour":[245],"large":[247],"cores":[249,269],"so":[251],"dominate":[252],"further":[257],"prevented.":[260],"operation":[263],"aggregation":[266],"proposed":[271],"overcome":[276],"associated":[278],"routing.":[280]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}