{"id":"https://openalex.org/W1495918396","doi":"https://doi.org/10.1109/fpt.2003.1275787","title":"Abstractions and primitives enabling runtime resource allocation for dynamic IP cores using virtual platform FPGAs","display_name":"Abstractions and primitives enabling runtime resource allocation for dynamic IP cores using virtual platform FPGAs","publication_year":2004,"publication_date":"2004-06-30","ids":{"openalex":"https://openalex.org/W1495918396","doi":"https://doi.org/10.1109/fpt.2003.1275787","mag":"1495918396"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2003.1275787","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2003.1275787","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048909297","display_name":"David Kearney","orcid":null},"institutions":[{"id":"https://openalex.org/I170239107","display_name":"University of South Australia","ror":"https://ror.org/01p93h210","country_code":"AU","type":"education","lineage":["https://openalex.org/I170239107"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"D.A. Kearney","raw_affiliation_strings":["Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia"],"affiliations":[{"raw_affiliation_string":"Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia","institution_ids":["https://openalex.org/I170239107"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022894130","display_name":"G. Veldman","orcid":null},"institutions":[{"id":"https://openalex.org/I170239107","display_name":"University of South Australia","ror":"https://ror.org/01p93h210","country_code":"AU","type":"education","lineage":["https://openalex.org/I170239107"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"G. Veldman","raw_affiliation_strings":["Reconfigurable Computing Laboratory (RCL), University of South Australia, Mawson Lakes SA, Australia","Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia"],"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Laboratory (RCL), University of South Australia, Mawson Lakes SA, Australia","institution_ids":["https://openalex.org/I170239107"]},{"raw_affiliation_string":"Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia","institution_ids":["https://openalex.org/I170239107"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055338447","display_name":"David S. Warren","orcid":"https://orcid.org/0000-0001-7567-8156"},"institutions":[{"id":"https://openalex.org/I170239107","display_name":"University of South Australia","ror":"https://ror.org/01p93h210","country_code":"AU","type":"education","lineage":["https://openalex.org/I170239107"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"D. Warren","raw_affiliation_strings":["Reconfigurable Computing Laboratory (RCL), University of South Australia, Mawson Lakes SA, Australia","Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia"],"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Laboratory (RCL), University of South Australia, Mawson Lakes SA, Australia","institution_ids":["https://openalex.org/I170239107"]},{"raw_affiliation_string":"Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia","institution_ids":["https://openalex.org/I170239107"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048909297"],"corresponding_institution_ids":["https://openalex.org/I170239107"],"apc_list":null,"apc_paid":null,"fwci":0.2317,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6007058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"403","last_page":"406"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8415502309799194},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7863483428955078},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6783527135848999},{"id":"https://openalex.org/keywords/programmer","display_name":"Programmer","score":0.6115371584892273},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.573149561882019},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5654615759849548},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5202228426933289},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4921981394290924},{"id":"https://openalex.org/keywords/runtime-system","display_name":"Runtime system","score":0.4566657841205597},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.43989044427871704},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.24404263496398926},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11741092801094055}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8415502309799194},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7863483428955078},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6783527135848999},{"id":"https://openalex.org/C2778514511","wikidata":"https://www.wikidata.org/wiki/Q1374194","display_name":"Programmer","level":2,"score":0.6115371584892273},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.573149561882019},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5654615759849548},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5202228426933289},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4921981394290924},{"id":"https://openalex.org/C2780870223","wikidata":"https://www.wikidata.org/wiki/Q1004415","display_name":"Runtime system","level":2,"score":0.4566657841205597},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.43989044427871704},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.24404263496398926},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11741092801094055},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2003.1275787","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2003.1275787","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1480258395","https://openalex.org/W1497161204","https://openalex.org/W2005262951","https://openalex.org/W2024939579","https://openalex.org/W2097869799","https://openalex.org/W2115121632","https://openalex.org/W2123654501","https://openalex.org/W2147359715","https://openalex.org/W2152926077","https://openalex.org/W2155255776","https://openalex.org/W2167408328","https://openalex.org/W6629768150","https://openalex.org/W6651698234"],"related_works":["https://openalex.org/W2204754129","https://openalex.org/W4322751528","https://openalex.org/W2759209791","https://openalex.org/W2340647897","https://openalex.org/W2500205862","https://openalex.org/W2760049414","https://openalex.org/W1569711686","https://openalex.org/W1541284233","https://openalex.org/W2808484818","https://openalex.org/W1574948540"],"abstract_inverted_index":{"The":[0,88],"platform":[1,38,74,80,102,135],"approach":[2,69],"to":[3,25,113],"hardware":[4],"design":[5,39],"was":[6],"originally":[7],"suggested":[8],"as":[9],"a":[10,18,72,78,85,123,133,138],"method":[11],"of":[12,16,37,46,48,84,93,98,105],"broadening":[13,43],"the":[14,35,41,44,94,106,115],"domain":[15],"applications":[17,47],"custom":[19],"VLSI":[20],"chip":[21],"can":[22],"be":[23],"applied":[24],"by":[26,50,70],"introducing":[27],"additional":[28],"programmability.":[29],"In":[30],"this":[31,68],"paper":[32,89],"we":[33,110],"extend":[34],"idea":[36],"with":[40],"objective":[42],"range":[45],"FPGAs":[49,57],"making":[51],"runtime":[52],"resource":[53],"allocation":[54],"available":[55],"for":[56,125,132],"that":[58,76,109,120,136],"do":[59],"not":[60],"support":[61],"run":[62],"time":[63],"reconfiguration":[64],"natively.":[65],"We":[66,118],"explore":[67],"constructing":[71],"virtual":[73,101,116,134],"FPGA;":[75],"is":[77,122],"reconfigurable":[79],"implemented":[81,112],"on":[82,148],"top":[83],"native":[86,150],"FPGA.":[87],"gives":[90],"an":[91],"overview":[92],"application":[95],"programmer's":[96],"interface":[97],"our":[99],"proposed":[100],"and":[103,144],"some":[104],"communication":[107],"primitives":[108,131],"have":[111],"construct":[114],"platform.":[117],"note":[119],"there":[121],"need":[124],"more":[126],"work":[127],"in":[128],"identifying":[129],"computation":[130],"strike":[137],"balance":[139],"between":[140],"supporting":[141],"useful":[142],"abstractions":[143],"having":[145],"efficient":[146],"implementations":[147],"typical":[149],"FPGAs.":[151]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}