{"id":"https://openalex.org/W2167711864","doi":"https://doi.org/10.1109/fpt.2003.1275744","title":"Product-term based synthesizable embedded programmable logic cores","display_name":"Product-term based synthesizable embedded programmable logic cores","publication_year":2004,"publication_date":"2004-06-30","ids":{"openalex":"https://openalex.org/W2167711864","doi":"https://doi.org/10.1109/fpt.2003.1275744","mag":"2167711864"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2003.1275744","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2003.1275744","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059698808","display_name":"Andy Yan","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Yan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S.J.E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.648,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.83307367,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"162","last_page":"169"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.7048730254173279},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7024409770965576},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6710202097892761},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.6510148048400879},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6368225812911987},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5881048440933228},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.5661832094192505},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5550414323806763},{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.5504858493804932},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5497869849205017},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5482379794120789},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4854870140552521},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.44650131464004517},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4460144340991974},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42458462715148926},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10296925902366638},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07966050505638123}],"concepts":[{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.7048730254173279},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7024409770965576},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6710202097892761},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.6510148048400879},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6368225812911987},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5881048440933228},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.5661832094192505},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5550414323806763},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.5504858493804932},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5497869849205017},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5482379794120789},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4854870140552521},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.44650131464004517},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4460144340991974},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42458462715148926},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10296925902366638},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07966050505638123},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpt.2003.1275744","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2003.1275744","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":71,"referenced_works":["https://openalex.org/W6850669","https://openalex.org/W7923187","https://openalex.org/W129209152","https://openalex.org/W1516835811","https://openalex.org/W1522950391","https://openalex.org/W1523051745","https://openalex.org/W1524957862","https://openalex.org/W1538922477","https://openalex.org/W1549045376","https://openalex.org/W1554938446","https://openalex.org/W1554946472","https://openalex.org/W1564421967","https://openalex.org/W1574542534","https://openalex.org/W1831088354","https://openalex.org/W1918461859","https://openalex.org/W1980746862","https://openalex.org/W1984954427","https://openalex.org/W1990161726","https://openalex.org/W2007249115","https://openalex.org/W2021709993","https://openalex.org/W2024060531","https://openalex.org/W2045726766","https://openalex.org/W2060499749","https://openalex.org/W2063435983","https://openalex.org/W2089710952","https://openalex.org/W2094806828","https://openalex.org/W2095565427","https://openalex.org/W2099229737","https://openalex.org/W2099502153","https://openalex.org/W2102872410","https://openalex.org/W2103223568","https://openalex.org/W2105715355","https://openalex.org/W2109656299","https://openalex.org/W2111945398","https://openalex.org/W2113669717","https://openalex.org/W2117492357","https://openalex.org/W2120397377","https://openalex.org/W2120428171","https://openalex.org/W2120780170","https://openalex.org/W2120791397","https://openalex.org/W2120985183","https://openalex.org/W2121369342","https://openalex.org/W2121903852","https://openalex.org/W2125609625","https://openalex.org/W2125990954","https://openalex.org/W2131385043","https://openalex.org/W2134066224","https://openalex.org/W2138840350","https://openalex.org/W2142033931","https://openalex.org/W2146056883","https://openalex.org/W2147419146","https://openalex.org/W2147648864","https://openalex.org/W2149518767","https://openalex.org/W2153819398","https://openalex.org/W2155833209","https://openalex.org/W2157373461","https://openalex.org/W2159190350","https://openalex.org/W2162002393","https://openalex.org/W2162546785","https://openalex.org/W2163996522","https://openalex.org/W2169333805","https://openalex.org/W2169528473","https://openalex.org/W2171679639","https://openalex.org/W2171775842","https://openalex.org/W2177095534","https://openalex.org/W2245562376","https://openalex.org/W2275304190","https://openalex.org/W2541217327","https://openalex.org/W2564921634","https://openalex.org/W4246775085","https://openalex.org/W6676280906"],"related_works":["https://openalex.org/W3013792460","https://openalex.org/W1904803855","https://openalex.org/W2376859467","https://openalex.org/W4389045693","https://openalex.org/W2374125170","https://openalex.org/W2990957507","https://openalex.org/W1839326631","https://openalex.org/W2360552902","https://openalex.org/W2169333805","https://openalex.org/W1983660943"],"abstract_inverted_index":{"As":[0],"integrated":[1,60],"circuits":[2],"become":[3,13],"increasingly":[4],"complex,":[5],"the":[6,35,59,64,91,109],"ability":[7,19],"to":[8,105],"make":[9],"post-fabrication":[10],"changes":[11],"will":[12],"more":[14],"important":[15],"and":[16,58,118],"attractive.":[17],"This":[18,71],"can":[20],"be":[21],"realized":[22],"using":[23,68],"programmable":[24,55,65],"logic":[25,56,66],"cores.":[26],"Currently,":[27],"such":[28],"cores":[29],"are":[30],"available":[31],"from":[32],"vendors":[33,48],"in":[34,113],"form":[36],"of":[37,53,77,94,101,116,121],"a":[38,50,74,99],"\"hard\"":[39],"layout.":[40],"Previous":[41],"work":[42],"has":[43],"suggested":[44],"an":[45],"alternative":[46],"approach:":[47],"supply":[49],"synthesizable":[51,81],"version":[52],"their":[54],"core":[57],"circuit":[61],"designer":[62],"synthesizes":[63],"fabric":[67],"standard":[69,124],"cells.":[70],"paper":[72],"presents":[73],"new":[75,92,110],"family":[76,93],"architectures":[78,85,95,111],"for":[79],"these":[80],"cores;":[82],"unlike":[83],"previous":[84],"which":[86],"were":[87],"based":[88,97,107],"on":[89,98,123],"lookup-tables,":[90],"is":[96],"collection":[100],"product-term":[102],"arrays.":[103],"Compared":[104],"lookup-table":[106],"architectures,":[108],"result":[112],"density":[114],"improvements":[115,120],"35%":[117],"speed":[119],"72%":[122],"benchmark":[125],"circuits.":[126]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
